Lines Matching +full:0 +full:x40b0
44 .l_reg = 0x0004,
45 .m_reg = 0x0008,
46 .n_reg = 0x000c,
47 .config_reg = 0x0014,
48 .mode_reg = 0x0000,
49 .status_reg = 0x001c,
62 .enable_reg = 0x0100,
63 .enable_mask = BIT(0),
75 .l_reg = 0x0044,
76 .m_reg = 0x0048,
77 .n_reg = 0x004c,
78 .config_reg = 0x0050,
79 .mode_reg = 0x0040,
80 .status_reg = 0x005c,
93 .enable_reg = 0x0100,
106 .l_reg = 0x4104,
107 .m_reg = 0x4108,
108 .n_reg = 0x410c,
109 .config_reg = 0x4110,
110 .mode_reg = 0x4100,
111 .status_reg = 0x411c,
123 .l_reg = 0x0084,
124 .m_reg = 0x0088,
125 .n_reg = 0x008c,
126 .config_reg = 0x0090,
127 .mode_reg = 0x0080,
128 .status_reg = 0x009c,
141 .l_reg = 0x00a4,
142 .m_reg = 0x00a8,
143 .n_reg = 0x00ac,
144 .config_reg = 0x00b0,
145 .mode_reg = 0x0080,
146 .status_reg = 0x00bc,
158 { P_XO, 0 },
172 { P_XO, 0 },
190 { P_XO, 0 },
206 { P_XO, 0 },
222 { P_XO, 0 },
240 { P_XO, 0 },
258 { P_XO, 0 },
276 { P_XO, 0 },
292 { P_XO, 0 },
310 { P_XO, 0 },
330 .cmd_rcgr = 0x5000,
342 F(19200000, P_XO, 1, 0, 0),
343 F(37500000, P_GPLL0, 16, 0, 0),
344 F(50000000, P_GPLL0, 12, 0, 0),
345 F(75000000, P_GPLL0, 8, 0, 0),
346 F(100000000, P_GPLL0, 6, 0, 0),
347 F(150000000, P_GPLL0, 4, 0, 0),
348 F(333430000, P_MMPLL1, 3.5, 0, 0),
349 F(400000000, P_MMPLL0, 2, 0, 0),
350 F(466800000, P_MMPLL1, 2.5, 0, 0),
354 .cmd_rcgr = 0x5040,
367 F(19200000, P_XO, 1, 0, 0),
368 F(37500000, P_GPLL0, 16, 0, 0),
369 F(50000000, P_GPLL0, 12, 0, 0),
370 F(75000000, P_GPLL0, 8, 0, 0),
371 F(109090000, P_GPLL0, 5.5, 0, 0),
372 F(150000000, P_GPLL0, 4, 0, 0),
373 F(228570000, P_MMPLL0, 3.5, 0, 0),
374 F(320000000, P_MMPLL0, 2.5, 0, 0),
378 .cmd_rcgr = 0x5090,
391 F(100000000, P_GPLL0, 6, 0, 0),
392 F(200000000, P_MMPLL0, 4, 0, 0),
397 .cmd_rcgr = 0x3090,
410 .cmd_rcgr = 0x3100,
423 .cmd_rcgr = 0x3160,
436 .cmd_rcgr = 0x31c0,
449 F(37500000, P_GPLL0, 16, 0, 0),
450 F(50000000, P_GPLL0, 12, 0, 0),
451 F(60000000, P_GPLL0, 10, 0, 0),
452 F(80000000, P_GPLL0, 7.5, 0, 0),
453 F(100000000, P_GPLL0, 6, 0, 0),
454 F(109090000, P_GPLL0, 5.5, 0, 0),
455 F(133330000, P_GPLL0, 4.5, 0, 0),
456 F(200000000, P_GPLL0, 3, 0, 0),
457 F(228570000, P_MMPLL0, 3.5, 0, 0),
458 F(266670000, P_MMPLL0, 3, 0, 0),
459 F(320000000, P_MMPLL0, 2.5, 0, 0),
460 F(465000000, P_MMPLL4, 2, 0, 0),
461 F(600000000, P_GPLL0, 1, 0, 0),
466 .cmd_rcgr = 0x3600,
479 .cmd_rcgr = 0x3620,
492 F(37500000, P_GPLL0, 16, 0, 0),
493 F(60000000, P_GPLL0, 10, 0, 0),
494 F(75000000, P_GPLL0, 8, 0, 0),
495 F(85710000, P_GPLL0, 7, 0, 0),
496 F(100000000, P_GPLL0, 6, 0, 0),
497 F(150000000, P_GPLL0, 4, 0, 0),
498 F(160000000, P_MMPLL0, 5, 0, 0),
499 F(200000000, P_MMPLL0, 4, 0, 0),
500 F(228570000, P_MMPLL0, 3.5, 0, 0),
501 F(300000000, P_GPLL0, 2, 0, 0),
502 F(320000000, P_MMPLL0, 2.5, 0, 0),
507 .cmd_rcgr = 0x2040,
520 .cmd_rcgr = 0x4000,
532 F(75000000, P_GPLL0, 8, 0, 0),
533 F(133330000, P_GPLL0, 4.5, 0, 0),
534 F(200000000, P_GPLL0, 3, 0, 0),
535 F(228570000, P_MMPLL0, 3.5, 0, 0),
536 F(266670000, P_MMPLL0, 3, 0, 0),
537 F(320000000, P_MMPLL0, 2.5, 0, 0),
542 .cmd_rcgr = 0x3500,
555 .cmd_rcgr = 0x3520,
568 .cmd_rcgr = 0x3540,
581 .cmd_rcgr = 0x2000,
595 .cmd_rcgr = 0x2020,
609 F(50000000, P_GPLL0, 12, 0, 0),
610 F(100000000, P_GPLL0, 6, 0, 0),
611 F(133330000, P_GPLL0, 4.5, 0, 0),
612 F(200000000, P_MMPLL0, 4, 0, 0),
613 F(266670000, P_MMPLL0, 3, 0, 0),
614 F(465000000, P_MMPLL3, 2, 0, 0),
619 .cmd_rcgr = 0x1000,
633 F(150000000, P_GPLL0, 4, 0, 0),
634 F(320000000, P_MMPLL0, 2.5, 0, 0),
639 .cmd_rcgr = 0x2430,
652 F(19200000, P_XO, 1, 0, 0),
657 .cmd_rcgr = 0x3300,
681 .cmd_rcgr = 0x3420,
695 .cmd_rcgr = 0x3450,
709 F(4800000, P_XO, 4, 0, 0),
712 F(9600000, P_XO, 2, 0, 0),
714 F(19200000, P_XO, 1, 0, 0),
717 F(48000000, P_GPLL0, 12.5, 0, 0),
718 F(64000000, P_MMPLL0, 12.5, 0, 0),
723 .cmd_rcgr = 0x3360,
737 .cmd_rcgr = 0x3390,
751 .cmd_rcgr = 0x33c0,
765 .cmd_rcgr = 0x33f0,
779 F(100000000, P_GPLL0, 6, 0, 0),
780 F(200000000, P_MMPLL0, 4, 0, 0),
785 .cmd_rcgr = 0x3000,
798 .cmd_rcgr = 0x3030,
811 .cmd_rcgr = 0x3060,
824 F(133330000, P_GPLL0, 4.5, 0, 0),
825 F(266670000, P_MMPLL0, 3, 0, 0),
826 F(320000000, P_MMPLL0, 2.5, 0, 0),
827 F(372000000, P_MMPLL4, 2.5, 0, 0),
828 F(465000000, P_MMPLL4, 2, 0, 0),
829 F(600000000, P_GPLL0, 1, 0, 0),
834 .cmd_rcgr = 0x3640,
847 .cmd_rcgr = 0x2120,
860 .cmd_rcgr = 0x2140,
873 F(19200000, P_XO, 1, 0, 0),
878 .cmd_rcgr = 0x20e0,
891 F(135000000, P_EDPLINK, 2, 0, 0),
892 F(270000000, P_EDPLINK, 11, 0, 0),
897 .cmd_rcgr = 0x20c0,
916 .cmd_rcgr = 0x20a0,
930 F(19200000, P_XO, 1, 0, 0),
935 .cmd_rcgr = 0x2160,
948 .cmd_rcgr = 0x2180,
966 .cmd_rcgr = 0x2060,
980 F(19200000, P_XO, 1, 0, 0),
985 .cmd_rcgr = 0x2100,
998 F(19200000, P_XO, 1, 0, 0),
1003 .cmd_rcgr = 0x2080,
1016 F(50000000, P_GPLL0, 12, 0, 0),
1021 .cmd_rcgr = 0x4060,
1034 F(19200000, P_XO, 1, 0, 0),
1039 .cmd_rcgr = 0x4090,
1052 F(50000000, P_GPLL0, 12, 0, 0),
1053 F(100000000, P_GPLL0, 6, 0, 0),
1054 F(133330000, P_GPLL0, 4.5, 0, 0),
1055 F(200000000, P_MMPLL0, 4, 0, 0),
1056 F(266670000, P_MMPLL0, 3, 0, 0),
1057 F(465000000, P_MMPLL3, 2, 0, 0),
1062 .cmd_rcgr = 0x1320,
1075 F(50000000, P_GPLL0, 12, 0, 0),
1076 F(100000000, P_GPLL0, 6, 0, 0),
1077 F(200000000, P_MMPLL0, 4, 0, 0),
1078 F(320000000, P_MMPLL0, 2.5, 0, 0),
1079 F(400000000, P_MMPLL0, 2, 0, 0),
1084 .cmd_rcgr = 0x1300,
1097 F(40000000, P_GPLL0, 15, 0, 0),
1098 F(80000000, P_MMPLL0, 10, 0, 0),
1103 .cmd_rcgr = 0x1340,
1116 .halt_reg = 0x5104,
1118 .enable_reg = 0x5104,
1119 .enable_mask = BIT(0),
1133 .halt_reg = 0x5100,
1135 .enable_reg = 0x5100,
1136 .enable_mask = BIT(0),
1150 .halt_reg = 0x2414,
1152 .enable_reg = 0x2414,
1153 .enable_mask = BIT(0),
1167 .halt_reg = 0x2418,
1169 .enable_reg = 0x2418,
1170 .enable_mask = BIT(0),
1184 .halt_reg = 0x2410,
1186 .enable_reg = 0x2410,
1187 .enable_mask = BIT(0),
1201 .halt_reg = 0x241c,
1203 .enable_reg = 0x241c,
1204 .enable_mask = BIT(0),
1218 .halt_reg = 0x2420,
1220 .enable_reg = 0x2420,
1221 .enable_mask = BIT(0),
1235 .halt_reg = 0x2404,
1237 .enable_reg = 0x2404,
1238 .enable_mask = BIT(0),
1252 .halt_reg = 0x348c,
1254 .enable_reg = 0x348c,
1255 .enable_mask = BIT(0),
1269 .halt_reg = 0x3348,
1271 .enable_reg = 0x3348,
1272 .enable_mask = BIT(0),
1285 .halt_reg = 0x3344,
1287 .enable_reg = 0x3344,
1288 .enable_mask = BIT(0),
1302 .halt_reg = 0x30bc,
1304 .enable_reg = 0x30bc,
1305 .enable_mask = BIT(0),
1318 .halt_reg = 0x30b4,
1320 .enable_reg = 0x30b4,
1321 .enable_mask = BIT(0),
1335 .halt_reg = 0x30c4,
1337 .enable_reg = 0x30c4,
1338 .enable_mask = BIT(0),
1352 .halt_reg = 0x30e4,
1354 .enable_reg = 0x30e4,
1355 .enable_mask = BIT(0),
1369 .halt_reg = 0x30d4,
1371 .enable_reg = 0x30d4,
1372 .enable_mask = BIT(0),
1386 .halt_reg = 0x3128,
1388 .enable_reg = 0x3128,
1389 .enable_mask = BIT(0),
1403 .halt_reg = 0x3124,
1405 .enable_reg = 0x3124,
1406 .enable_mask = BIT(0),
1420 .halt_reg = 0x3134,
1422 .enable_reg = 0x3134,
1423 .enable_mask = BIT(0),
1437 .halt_reg = 0x3154,
1439 .enable_reg = 0x3154,
1440 .enable_mask = BIT(0),
1454 .halt_reg = 0x3144,
1456 .enable_reg = 0x3144,
1457 .enable_mask = BIT(0),
1471 .halt_reg = 0x3188,
1473 .enable_reg = 0x3188,
1474 .enable_mask = BIT(0),
1487 .halt_reg = 0x3184,
1489 .enable_reg = 0x3184,
1490 .enable_mask = BIT(0),
1504 .halt_reg = 0x3194,
1506 .enable_reg = 0x3194,
1507 .enable_mask = BIT(0),
1521 .halt_reg = 0x31b4,
1523 .enable_reg = 0x31b4,
1524 .enable_mask = BIT(0),
1538 .halt_reg = 0x31a4,
1540 .enable_reg = 0x31a4,
1541 .enable_mask = BIT(0),
1555 .halt_reg = 0x31e8,
1557 .enable_reg = 0x31e8,
1558 .enable_mask = BIT(0),
1571 .halt_reg = 0x31e4,
1573 .enable_reg = 0x31e4,
1574 .enable_mask = BIT(0),
1588 .halt_reg = 0x31f4,
1590 .enable_reg = 0x31f4,
1591 .enable_mask = BIT(0),
1605 .halt_reg = 0x3214,
1607 .enable_reg = 0x3214,
1608 .enable_mask = BIT(0),
1622 .halt_reg = 0x3204,
1624 .enable_reg = 0x3204,
1625 .enable_mask = BIT(0),
1639 .halt_reg = 0x3704,
1641 .enable_reg = 0x3704,
1642 .enable_mask = BIT(0),
1656 .halt_reg = 0x3714,
1658 .enable_reg = 0x3714,
1659 .enable_mask = BIT(0),
1673 .halt_reg = 0x3444,
1675 .enable_reg = 0x3444,
1676 .enable_mask = BIT(0),
1690 .halt_reg = 0x3474,
1692 .enable_reg = 0x3474,
1693 .enable_mask = BIT(0),
1707 .halt_reg = 0x3224,
1709 .enable_reg = 0x3224,
1710 .enable_mask = BIT(0),
1724 .halt_reg = 0x35a8,
1726 .enable_reg = 0x35a8,
1727 .enable_mask = BIT(0),
1741 .halt_reg = 0x35ac,
1743 .enable_reg = 0x35ac,
1744 .enable_mask = BIT(0),
1758 .halt_reg = 0x35b0,
1760 .enable_reg = 0x35b0,
1761 .enable_mask = BIT(0),
1775 .halt_reg = 0x35b4,
1777 .enable_reg = 0x35b4,
1778 .enable_mask = BIT(0),
1791 .halt_reg = 0x35b8,
1793 .enable_reg = 0x35b8,
1794 .enable_mask = BIT(0),
1807 .halt_reg = 0x3384,
1809 .enable_reg = 0x3384,
1810 .enable_mask = BIT(0),
1824 .halt_reg = 0x33b4,
1826 .enable_reg = 0x33b4,
1827 .enable_mask = BIT(0),
1841 .halt_reg = 0x33e4,
1843 .enable_reg = 0x33e4,
1844 .enable_mask = BIT(0),
1858 .halt_reg = 0x3414,
1860 .enable_reg = 0x3414,
1861 .enable_mask = BIT(0),
1875 .halt_reg = 0x3494,
1877 .enable_reg = 0x3494,
1878 .enable_mask = BIT(0),
1891 .halt_reg = 0x3024,
1893 .enable_reg = 0x3024,
1894 .enable_mask = BIT(0),
1908 .halt_reg = 0x3054,
1910 .enable_reg = 0x3054,
1911 .enable_mask = BIT(0),
1925 .halt_reg = 0x3084,
1927 .enable_reg = 0x3084,
1928 .enable_mask = BIT(0),
1942 .halt_reg = 0x3484,
1944 .enable_reg = 0x3484,
1945 .enable_mask = BIT(0),
1959 .halt_reg = 0x36b4,
1961 .enable_reg = 0x36b4,
1962 .enable_mask = BIT(0),
1976 .halt_reg = 0x36b0,
1978 .enable_reg = 0x36b0,
1979 .enable_mask = BIT(0),
1993 .halt_reg = 0x36a8,
1995 .enable_reg = 0x36a8,
1996 .enable_mask = BIT(0),
2010 .halt_reg = 0x36ac,
2012 .enable_reg = 0x36ac,
2013 .enable_mask = BIT(0),
2027 .halt_reg = 0x36b8,
2029 .enable_reg = 0x36b8,
2030 .enable_mask = BIT(0),
2044 .halt_reg = 0x36bc,
2046 .enable_reg = 0x36bc,
2047 .enable_mask = BIT(0),
2061 .halt_reg = 0x2308,
2063 .enable_reg = 0x2308,
2064 .enable_mask = BIT(0),
2078 .halt_reg = 0x2310,
2080 .enable_reg = 0x2310,
2081 .enable_mask = BIT(0),
2095 .halt_reg = 0x233c,
2097 .enable_reg = 0x233c,
2098 .enable_mask = BIT(0),
2112 .halt_reg = 0x2340,
2114 .enable_reg = 0x2340,
2115 .enable_mask = BIT(0),
2129 .halt_reg = 0x2334,
2131 .enable_reg = 0x2334,
2132 .enable_mask = BIT(0),
2146 .halt_reg = 0x2330,
2148 .enable_reg = 0x2330,
2149 .enable_mask = BIT(0),
2163 .halt_reg = 0x232c,
2165 .enable_reg = 0x232c,
2166 .enable_mask = BIT(0),
2180 .halt_reg = 0x2344,
2182 .enable_reg = 0x2344,
2183 .enable_mask = BIT(0),
2197 .halt_reg = 0x2348,
2199 .enable_reg = 0x2348,
2200 .enable_mask = BIT(0),
2214 .halt_reg = 0x2324,
2216 .enable_reg = 0x2324,
2217 .enable_mask = BIT(0),
2231 .halt_reg = 0x230c,
2233 .enable_reg = 0x230c,
2234 .enable_mask = BIT(0),
2248 .halt_reg = 0x2338,
2250 .enable_reg = 0x2338,
2251 .enable_mask = BIT(0),
2265 .halt_reg = 0x231c,
2267 .enable_reg = 0x231c,
2268 .enable_mask = BIT(0),
2282 .halt_reg = 0x2320,
2284 .enable_reg = 0x2320,
2285 .enable_mask = BIT(0),
2299 .halt_reg = 0x2314,
2301 .enable_reg = 0x2314,
2302 .enable_mask = BIT(0),
2316 .halt_reg = 0x2318,
2318 .enable_reg = 0x2318,
2319 .enable_mask = BIT(0),
2333 .halt_reg = 0x2328,
2335 .enable_reg = 0x2328,
2336 .enable_mask = BIT(0),
2350 .halt_reg = 0x4088,
2352 .enable_reg = 0x4088,
2353 .enable_mask = BIT(0),
2367 .halt_reg = 0x4084,
2369 .enable_reg = 0x4084,
2370 .enable_mask = BIT(0),
2384 .halt_reg = 0x502c,
2386 .enable_reg = 0x502c,
2387 .enable_mask = BIT(0),
2401 .halt_reg = 0x5024,
2403 .enable_reg = 0x5024,
2404 .enable_mask = BIT(0),
2418 .halt_reg = 0x5028,
2420 .enable_reg = 0x5028,
2421 .enable_mask = BIT(0),
2435 .halt_reg = 0x506c,
2437 .enable_reg = 0x506c,
2438 .enable_mask = BIT(0),
2452 .halt_reg = 0x5064,
2454 .enable_reg = 0x5064,
2455 .enable_mask = BIT(0),
2469 .halt_reg = 0x405c,
2471 .enable_reg = 0x405c,
2472 .enable_mask = BIT(0),
2486 .halt_reg = 0x4058,
2488 .enable_reg = 0x4058,
2489 .enable_mask = BIT(0),
2503 .halt_reg = 0x402c,
2505 .enable_reg = 0x402c,
2506 .enable_mask = BIT(0),
2520 .halt_reg = 0x4028,
2522 .enable_reg = 0x4028,
2523 .enable_mask = BIT(0),
2537 .halt_reg = 0x40b0,
2539 .enable_reg = 0x40b0,
2540 .enable_mask = BIT(0),
2554 .halt_reg = 0x403c,
2556 .enable_reg = 0x403c,
2557 .enable_mask = BIT(0),
2571 .halt_reg = 0x1030,
2573 .enable_reg = 0x1030,
2574 .enable_mask = BIT(0),
2588 .halt_reg = 0x1034,
2590 .enable_reg = 0x1034,
2591 .enable_mask = BIT(0),
2605 .halt_reg = 0x1048,
2607 .enable_reg = 0x1048,
2608 .enable_mask = BIT(0),
2622 .halt_reg = 0x104c,
2624 .enable_reg = 0x104c,
2625 .enable_mask = BIT(0),
2639 .halt_reg = 0x1038,
2641 .enable_reg = 0x1038,
2642 .enable_mask = BIT(0),
2656 .halt_reg = 0x1028,
2658 .enable_reg = 0x1028,
2659 .enable_mask = BIT(0),
2673 .halt_reg = 0x1430,
2675 .enable_reg = 0x1430,
2676 .enable_mask = BIT(0),
2690 .halt_reg = 0x143c,
2692 .enable_reg = 0x143c,
2693 .enable_mask = BIT(0),
2707 .halt_reg = 0x1440,
2709 .enable_reg = 0x1440,
2710 .enable_mask = BIT(0),
2724 .halt_reg = 0x1434,
2726 .enable_reg = 0x1434,
2727 .enable_mask = BIT(0),
2741 .halt_reg = 0x142c,
2743 .enable_reg = 0x142c,
2744 .enable_mask = BIT(0),
2758 .halt_reg = 0x1438,
2760 .enable_reg = 0x1438,
2761 .enable_mask = BIT(0),
2775 .halt_reg = 0x1428,
2777 .enable_reg = 0x1428,
2778 .enable_mask = BIT(0),
2795 .vco_val = 0x0,
2796 .vco_mask = 0x3 << 20,
2797 .pre_div_val = 0x0,
2798 .pre_div_mask = 0x7 << 12,
2799 .post_div_val = 0x0,
2800 .post_div_mask = 0x3 << 8,
2802 .main_output_mask = BIT(0),
2809 .vco_val = 0x0,
2810 .vco_mask = 0x3 << 20,
2811 .pre_div_val = 0x0,
2812 .pre_div_mask = 0x7 << 12,
2813 .post_div_val = 0x0,
2814 .post_div_mask = 0x3 << 8,
2816 .main_output_mask = BIT(0),
2821 .gdscr = 0x1024,
2829 .gdscr = 0x1040,
2837 .gdscr = 0x1044,
2845 .gdscr = 0x2304,
2846 .cxcs = (unsigned int []){ 0x231c, 0x2320 },
2855 .gdscr = 0x35a4,
2863 .gdscr = 0x36a4,
2864 .cxcs = (unsigned int []){ 0x36a8, 0x36ac, 0x36b0 },
2873 .gdscr = 0x4024,
2874 .cxcs = (unsigned int []){ 0x4028 },
2883 .gdscr = 0x4034,
3044 [MMSS_SPDM_RESET] = { 0x0200 },
3045 [MMSS_SPDM_RM_RESET] = { 0x0300 },
3046 [VENUS0_RESET] = { 0x1020 },
3047 [VPU_RESET] = { 0x1400 },
3048 [MDSS_RESET] = { 0x2300 },
3049 [AVSYNC_RESET] = { 0x2400 },
3050 [CAMSS_PHY0_RESET] = { 0x3020 },
3051 [CAMSS_PHY1_RESET] = { 0x3050 },
3052 [CAMSS_PHY2_RESET] = { 0x3080 },
3053 [CAMSS_CSI0_RESET] = { 0x30b0 },
3054 [CAMSS_CSI0PHY_RESET] = { 0x30c0 },
3055 [CAMSS_CSI0RDI_RESET] = { 0x30d0 },
3056 [CAMSS_CSI0PIX_RESET] = { 0x30e0 },
3057 [CAMSS_CSI1_RESET] = { 0x3120 },
3058 [CAMSS_CSI1PHY_RESET] = { 0x3130 },
3059 [CAMSS_CSI1RDI_RESET] = { 0x3140 },
3060 [CAMSS_CSI1PIX_RESET] = { 0x3150 },
3061 [CAMSS_CSI2_RESET] = { 0x3180 },
3062 [CAMSS_CSI2PHY_RESET] = { 0x3190 },
3063 [CAMSS_CSI2RDI_RESET] = { 0x31a0 },
3064 [CAMSS_CSI2PIX_RESET] = { 0x31b0 },
3065 [CAMSS_CSI3_RESET] = { 0x31e0 },
3066 [CAMSS_CSI3PHY_RESET] = { 0x31f0 },
3067 [CAMSS_CSI3RDI_RESET] = { 0x3200 },
3068 [CAMSS_CSI3PIX_RESET] = { 0x3210 },
3069 [CAMSS_ISPIF_RESET] = { 0x3220 },
3070 [CAMSS_CCI_RESET] = { 0x3340 },
3071 [CAMSS_MCLK0_RESET] = { 0x3380 },
3072 [CAMSS_MCLK1_RESET] = { 0x33b0 },
3073 [CAMSS_MCLK2_RESET] = { 0x33e0 },
3074 [CAMSS_MCLK3_RESET] = { 0x3410 },
3075 [CAMSS_GP0_RESET] = { 0x3440 },
3076 [CAMSS_GP1_RESET] = { 0x3470 },
3077 [CAMSS_TOP_RESET] = { 0x3480 },
3078 [CAMSS_AHB_RESET] = { 0x3488 },
3079 [CAMSS_MICRO_RESET] = { 0x3490 },
3080 [CAMSS_JPEG_RESET] = { 0x35a0 },
3081 [CAMSS_VFE_RESET] = { 0x36a0 },
3082 [CAMSS_CSI_VFE0_RESET] = { 0x3700 },
3083 [CAMSS_CSI_VFE1_RESET] = { 0x3710 },
3084 [OXILI_RESET] = { 0x4020 },
3085 [OXILICX_RESET] = { 0x4030 },
3086 [OCMEMCX_RESET] = { 0x4050 },
3087 [MMSS_RBCRP_RESET] = { 0x4080 },
3088 [MMSSNOCAHB_RESET] = { 0x5020 },
3089 [MMSSNOCAXI_RESET] = { 0x5060 },
3107 .max_register = 0x5104,
3140 return 0; in mmcc_apq8084_probe()