Lines Matching +full:edma +full:- +full:tx
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * drivers/dma/fsl-edma.c
5 * Copyright 2013-2014 Freescale Semiconductor, Inc.
7 * Driver for the Freescale eDMA engine with flexible channel multiplexing
8 * capability for DMA request sources. The eDMA block can be found on some
12 #include <dt-bindings/dma/fsl-edma.h>
22 #include <linux/dma-mapping.h>
26 #include "fsl-edma-common.h"
32 vchan_synchronize(&fsl_chan->vchan); in fsl_edma_synchronize()
39 struct edma_regs *regs = &fsl_edma->regs; in fsl_edma_tx_handler()
41 intr = edma_readl(fsl_edma, regs->intl); in fsl_edma_tx_handler()
45 for (ch = 0; ch < fsl_edma->n_chans; ch++) { in fsl_edma_tx_handler()
47 edma_writeb(fsl_edma, EDMA_CINT_CINT(ch), regs->cint); in fsl_edma_tx_handler()
48 fsl_edma_tx_chan_handler(&fsl_edma->chans[ch]); in fsl_edma_tx_handler()
74 struct edma_regs *regs = &fsl_edma->regs; in fsl_edma_err_handler()
76 err = edma_readl(fsl_edma, regs->errl); in fsl_edma_err_handler()
80 for (ch = 0; ch < fsl_edma->n_chans; ch++) { in fsl_edma_err_handler()
82 fsl_edma_disable_request(&fsl_edma->chans[ch]); in fsl_edma_err_handler()
83 edma_writeb(fsl_edma, EDMA_CERR_CERR(ch), regs->cerr); in fsl_edma_err_handler()
84 fsl_edma_err_chan_handler(&fsl_edma->chans[ch]); in fsl_edma_err_handler()
101 struct fsl_edma_engine *fsl_edma = ofdma->of_dma_data; in fsl_edma_xlate()
104 u32 dmamux_nr = fsl_edma->drvdata->dmamuxs; in fsl_edma_xlate()
105 unsigned long chans_per_mux = fsl_edma->n_chans / dmamux_nr; in fsl_edma_xlate()
107 if (dma_spec->args_count != 2) in fsl_edma_xlate()
110 mutex_lock(&fsl_edma->fsl_edma_mutex); in fsl_edma_xlate()
111 list_for_each_entry_safe(chan, _chan, &fsl_edma->dma_dev.channels, device_node) { in fsl_edma_xlate()
112 if (chan->client_count) in fsl_edma_xlate()
114 if ((chan->chan_id / chans_per_mux) == dma_spec->args[0]) { in fsl_edma_xlate()
117 chan->device->privatecnt++; in fsl_edma_xlate()
119 fsl_chan->slave_id = dma_spec->args[1]; in fsl_edma_xlate()
120 fsl_edma_chan_mux(fsl_chan, fsl_chan->slave_id, in fsl_edma_xlate()
122 mutex_unlock(&fsl_edma->fsl_edma_mutex); in fsl_edma_xlate()
127 mutex_unlock(&fsl_edma->fsl_edma_mutex); in fsl_edma_xlate()
134 struct fsl_edma_engine *fsl_edma = ofdma->of_dma_data; in fsl_edma3_xlate()
140 if (dma_spec->args_count != 3) in fsl_edma3_xlate()
143 b_chmux = !!(fsl_edma->drvdata->flags & FSL_EDMA_DRV_HAS_CHMUX); in fsl_edma3_xlate()
145 mutex_lock(&fsl_edma->fsl_edma_mutex); in fsl_edma3_xlate()
146 list_for_each_entry_safe(chan, _chan, &fsl_edma->dma_dev.channels, in fsl_edma3_xlate()
149 if (chan->client_count) in fsl_edma3_xlate()
153 i = fsl_chan - fsl_edma->chans; in fsl_edma3_xlate()
155 fsl_chan->priority = dma_spec->args[1]; in fsl_edma3_xlate()
156 fsl_chan->is_rxchan = dma_spec->args[2] & FSL_EDMA_RX; in fsl_edma3_xlate()
157 fsl_chan->is_remote = dma_spec->args[2] & FSL_EDMA_REMOTE; in fsl_edma3_xlate()
158 fsl_chan->is_multi_fifo = dma_spec->args[2] & FSL_EDMA_MULTI_FIFO; in fsl_edma3_xlate()
160 if ((dma_spec->args[2] & FSL_EDMA_EVEN_CH) && (i & 0x1)) in fsl_edma3_xlate()
163 if ((dma_spec->args[2] & FSL_EDMA_ODD_CH) && !(i & 0x1)) in fsl_edma3_xlate()
166 if (!b_chmux && i == dma_spec->args[0]) { in fsl_edma3_xlate()
168 chan->device->privatecnt++; in fsl_edma3_xlate()
169 mutex_unlock(&fsl_edma->fsl_edma_mutex); in fsl_edma3_xlate()
171 } else if (b_chmux && !fsl_chan->srcid) { in fsl_edma3_xlate()
174 chan->device->privatecnt++; in fsl_edma3_xlate()
175 fsl_chan->srcid = dma_spec->args[0]; in fsl_edma3_xlate()
176 mutex_unlock(&fsl_edma->fsl_edma_mutex); in fsl_edma3_xlate()
180 mutex_unlock(&fsl_edma->fsl_edma_mutex); in fsl_edma3_xlate()
189 edma_writel(fsl_edma, ~0, fsl_edma->regs.intl); in fsl_edma_irq_init()
191 fsl_edma->txirq = platform_get_irq_byname(pdev, "edma-tx"); in fsl_edma_irq_init()
192 if (fsl_edma->txirq < 0) in fsl_edma_irq_init()
193 return fsl_edma->txirq; in fsl_edma_irq_init()
195 fsl_edma->errirq = platform_get_irq_byname(pdev, "edma-err"); in fsl_edma_irq_init()
196 if (fsl_edma->errirq < 0) in fsl_edma_irq_init()
197 return fsl_edma->errirq; in fsl_edma_irq_init()
199 if (fsl_edma->txirq == fsl_edma->errirq) { in fsl_edma_irq_init()
200 ret = devm_request_irq(&pdev->dev, fsl_edma->txirq, in fsl_edma_irq_init()
201 fsl_edma_irq_handler, 0, "eDMA", fsl_edma); in fsl_edma_irq_init()
203 dev_err(&pdev->dev, "Can't register eDMA IRQ.\n"); in fsl_edma_irq_init()
207 ret = devm_request_irq(&pdev->dev, fsl_edma->txirq, in fsl_edma_irq_init()
208 fsl_edma_tx_handler, 0, "eDMA tx", fsl_edma); in fsl_edma_irq_init()
210 dev_err(&pdev->dev, "Can't register eDMA tx IRQ.\n"); in fsl_edma_irq_init()
214 ret = devm_request_irq(&pdev->dev, fsl_edma->errirq, in fsl_edma_irq_init()
215 fsl_edma_err_handler, 0, "eDMA err", fsl_edma); in fsl_edma_irq_init()
217 dev_err(&pdev->dev, "Can't register eDMA err IRQ.\n"); in fsl_edma_irq_init()
230 for (i = 0; i < fsl_edma->n_chans; i++) { in fsl_edma3_irq_init()
232 struct fsl_edma_chan *fsl_chan = &fsl_edma->chans[i]; in fsl_edma3_irq_init()
234 if (fsl_edma->chan_masked & BIT(i)) in fsl_edma3_irq_init()
238 fsl_chan->txirq = platform_get_irq(pdev, i); in fsl_edma3_irq_init()
239 if (fsl_chan->txirq < 0) { in fsl_edma3_irq_init()
240 dev_err(&pdev->dev, "Can't get chan %d's irq.\n", i); in fsl_edma3_irq_init()
241 return -EINVAL; in fsl_edma3_irq_init()
244 ret = devm_request_irq(&pdev->dev, fsl_chan->txirq, in fsl_edma3_irq_init()
246 fsl_chan->chan_name, fsl_chan); in fsl_edma3_irq_init()
248 dev_err(&pdev->dev, "Can't register chan%d's IRQ.\n", i); in fsl_edma3_irq_init()
249 return -EINVAL; in fsl_edma3_irq_init()
263 edma_writel(fsl_edma, ~0, fsl_edma->regs.intl); in fsl_edma2_irq_init()
266 dev_dbg(&pdev->dev, "%s Found %d interrupts\r\n", __func__, count); in fsl_edma2_irq_init()
268 dev_err(&pdev->dev, "Interrupts in DTS not correct.\n"); in fsl_edma2_irq_init()
269 return -EINVAL; in fsl_edma2_irq_init()
280 return -ENXIO; in fsl_edma2_irq_init()
282 /* The last IRQ is for eDMA err */ in fsl_edma2_irq_init()
283 if (i == count - 1) in fsl_edma2_irq_init()
284 ret = devm_request_irq(&pdev->dev, irq, in fsl_edma2_irq_init()
286 0, "eDMA2-ERR", fsl_edma); in fsl_edma2_irq_init()
288 ret = devm_request_irq(&pdev->dev, irq, in fsl_edma2_irq_init()
290 fsl_edma->chans[i].chan_name, in fsl_edma2_irq_init()
302 if (fsl_edma->txirq == fsl_edma->errirq) { in fsl_edma_irq_exit()
303 devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma); in fsl_edma_irq_exit()
305 devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma); in fsl_edma_irq_exit()
306 devm_free_irq(&pdev->dev, fsl_edma->errirq, fsl_edma); in fsl_edma_irq_exit()
315 clk_disable_unprepare(fsl_edma->muxclk[i]); in fsl_disable_clocks()
371 { .compatible = "fsl,vf610-edma", .data = &vf610_data},
372 { .compatible = "fsl,ls1028a-edma", .data = &ls1028a_data},
373 { .compatible = "fsl,imx7ulp-edma", .data = &imx7ulp_data},
374 { .compatible = "fsl,imx8qm-edma", .data = &imx8qm_data},
375 { .compatible = "fsl,imx8qm-adma", .data = &imx8qm_audio_data},
376 { .compatible = "fsl,imx93-edma3", .data = &imx93_data3},
377 { .compatible = "fsl,imx93-edma4", .data = &imx93_data4},
390 dev = &pdev->dev; in fsl_edma3_attach_pd()
392 for (i = 0; i < fsl_edma->n_chans; i++) { in fsl_edma3_attach_pd()
393 if (fsl_edma->chan_masked & BIT(i)) in fsl_edma3_attach_pd()
396 fsl_chan = &fsl_edma->chans[i]; in fsl_edma3_attach_pd()
401 return -EINVAL; in fsl_edma3_attach_pd()
409 return -EINVAL; in fsl_edma3_attach_pd()
412 fsl_chan->pd_dev = pd_chan; in fsl_edma3_attach_pd()
414 pm_runtime_use_autosuspend(fsl_chan->pd_dev); in fsl_edma3_attach_pd()
415 pm_runtime_set_autosuspend_delay(fsl_chan->pd_dev, 200); in fsl_edma3_attach_pd()
416 pm_runtime_set_active(fsl_chan->pd_dev); in fsl_edma3_attach_pd()
425 of_match_device(fsl_edma_dt_ids, &pdev->dev); in fsl_edma_probe()
426 struct device_node *np = pdev->dev.of_node; in fsl_edma_probe()
435 drvdata = of_id->data; in fsl_edma_probe()
437 dev_err(&pdev->dev, "unable to find driver data\n"); in fsl_edma_probe()
438 return -EINVAL; in fsl_edma_probe()
441 ret = of_property_read_u32(np, "dma-channels", &chans); in fsl_edma_probe()
443 dev_err(&pdev->dev, "Can't get dma-channels.\n"); in fsl_edma_probe()
447 fsl_edma = devm_kzalloc(&pdev->dev, struct_size(fsl_edma, chans, chans), in fsl_edma_probe()
450 return -ENOMEM; in fsl_edma_probe()
452 fsl_edma->drvdata = drvdata; in fsl_edma_probe()
453 fsl_edma->n_chans = chans; in fsl_edma_probe()
454 mutex_init(&fsl_edma->fsl_edma_mutex); in fsl_edma_probe()
456 fsl_edma->membase = devm_platform_ioremap_resource(pdev, 0); in fsl_edma_probe()
457 if (IS_ERR(fsl_edma->membase)) in fsl_edma_probe()
458 return PTR_ERR(fsl_edma->membase); in fsl_edma_probe()
460 if (!(drvdata->flags & FSL_EDMA_DRV_SPLIT_REG)) { in fsl_edma_probe()
462 regs = &fsl_edma->regs; in fsl_edma_probe()
465 if (drvdata->flags & FSL_EDMA_DRV_HAS_DMACLK) { in fsl_edma_probe()
466 fsl_edma->dmaclk = devm_clk_get_enabled(&pdev->dev, "dma"); in fsl_edma_probe()
467 if (IS_ERR(fsl_edma->dmaclk)) { in fsl_edma_probe()
468 dev_err(&pdev->dev, "Missing DMA block clock.\n"); in fsl_edma_probe()
469 return PTR_ERR(fsl_edma->dmaclk); in fsl_edma_probe()
473 if (drvdata->flags & FSL_EDMA_DRV_HAS_CHCLK) { in fsl_edma_probe()
474 fsl_edma->chclk = devm_clk_get_enabled(&pdev->dev, "mp"); in fsl_edma_probe()
475 if (IS_ERR(fsl_edma->chclk)) { in fsl_edma_probe()
476 dev_err(&pdev->dev, "Missing MP block clock.\n"); in fsl_edma_probe()
477 return PTR_ERR(fsl_edma->chclk); in fsl_edma_probe()
481 ret = of_property_read_variable_u32_array(np, "dma-channel-mask", chan_mask, 1, 2); in fsl_edma_probe()
484 fsl_edma->chan_masked = chan_mask[1]; in fsl_edma_probe()
485 fsl_edma->chan_masked <<= 32; in fsl_edma_probe()
486 fsl_edma->chan_masked |= chan_mask[0]; in fsl_edma_probe()
489 for (i = 0; i < fsl_edma->drvdata->dmamuxs; i++) { in fsl_edma_probe()
493 if (drvdata->flags & FSL_EDMA_DRV_SPLIT_REG) in fsl_edma_probe()
496 fsl_edma->muxbase[i] = devm_platform_ioremap_resource(pdev, in fsl_edma_probe()
498 if (IS_ERR(fsl_edma->muxbase[i])) { in fsl_edma_probe()
501 return PTR_ERR(fsl_edma->muxbase[i]); in fsl_edma_probe()
505 fsl_edma->muxclk[i] = devm_clk_get_enabled(&pdev->dev, clkname); in fsl_edma_probe()
506 if (IS_ERR(fsl_edma->muxclk[i])) { in fsl_edma_probe()
507 dev_err(&pdev->dev, "Missing DMAMUX block clock.\n"); in fsl_edma_probe()
509 return PTR_ERR(fsl_edma->muxclk[i]); in fsl_edma_probe()
513 fsl_edma->big_endian = of_property_read_bool(np, "big-endian"); in fsl_edma_probe()
515 if (drvdata->flags & FSL_EDMA_DRV_HAS_PD) { in fsl_edma_probe()
521 INIT_LIST_HEAD(&fsl_edma->dma_dev.channels); in fsl_edma_probe()
522 for (i = 0; i < fsl_edma->n_chans; i++) { in fsl_edma_probe()
523 struct fsl_edma_chan *fsl_chan = &fsl_edma->chans[i]; in fsl_edma_probe()
526 if (fsl_edma->chan_masked & BIT(i)) in fsl_edma_probe()
529 snprintf(fsl_chan->chan_name, sizeof(fsl_chan->chan_name), "%s-CH%02d", in fsl_edma_probe()
530 dev_name(&pdev->dev), i); in fsl_edma_probe()
532 fsl_chan->edma = fsl_edma; in fsl_edma_probe()
533 fsl_chan->pm_state = RUNNING; in fsl_edma_probe()
534 fsl_chan->slave_id = 0; in fsl_edma_probe()
535 fsl_chan->idle = true; in fsl_edma_probe()
536 fsl_chan->dma_dir = DMA_NONE; in fsl_edma_probe()
537 fsl_chan->vchan.desc_free = fsl_edma_free_desc; in fsl_edma_probe()
539 len = (drvdata->flags & FSL_EDMA_DRV_SPLIT_REG) ? in fsl_edma_probe()
541 fsl_chan->tcd = fsl_edma->membase in fsl_edma_probe()
542 + i * drvdata->chreg_space_sz + drvdata->chreg_off + len; in fsl_edma_probe()
544 fsl_chan->pdev = pdev; in fsl_edma_probe()
545 vchan_init(&fsl_chan->vchan, &fsl_edma->dma_dev); in fsl_edma_probe()
551 ret = fsl_edma->drvdata->setup_irq(pdev, fsl_edma); in fsl_edma_probe()
555 dma_cap_set(DMA_PRIVATE, fsl_edma->dma_dev.cap_mask); in fsl_edma_probe()
556 dma_cap_set(DMA_SLAVE, fsl_edma->dma_dev.cap_mask); in fsl_edma_probe()
557 dma_cap_set(DMA_CYCLIC, fsl_edma->dma_dev.cap_mask); in fsl_edma_probe()
558 dma_cap_set(DMA_MEMCPY, fsl_edma->dma_dev.cap_mask); in fsl_edma_probe()
560 fsl_edma->dma_dev.dev = &pdev->dev; in fsl_edma_probe()
561 fsl_edma->dma_dev.device_alloc_chan_resources in fsl_edma_probe()
563 fsl_edma->dma_dev.device_free_chan_resources in fsl_edma_probe()
565 fsl_edma->dma_dev.device_tx_status = fsl_edma_tx_status; in fsl_edma_probe()
566 fsl_edma->dma_dev.device_prep_slave_sg = fsl_edma_prep_slave_sg; in fsl_edma_probe()
567 fsl_edma->dma_dev.device_prep_dma_cyclic = fsl_edma_prep_dma_cyclic; in fsl_edma_probe()
568 fsl_edma->dma_dev.device_prep_dma_memcpy = fsl_edma_prep_memcpy; in fsl_edma_probe()
569 fsl_edma->dma_dev.device_config = fsl_edma_slave_config; in fsl_edma_probe()
570 fsl_edma->dma_dev.device_pause = fsl_edma_pause; in fsl_edma_probe()
571 fsl_edma->dma_dev.device_resume = fsl_edma_resume; in fsl_edma_probe()
572 fsl_edma->dma_dev.device_terminate_all = fsl_edma_terminate_all; in fsl_edma_probe()
573 fsl_edma->dma_dev.device_synchronize = fsl_edma_synchronize; in fsl_edma_probe()
574 fsl_edma->dma_dev.device_issue_pending = fsl_edma_issue_pending; in fsl_edma_probe()
576 fsl_edma->dma_dev.src_addr_widths = FSL_EDMA_BUSWIDTHS; in fsl_edma_probe()
577 fsl_edma->dma_dev.dst_addr_widths = FSL_EDMA_BUSWIDTHS; in fsl_edma_probe()
579 if (drvdata->flags & FSL_EDMA_DRV_BUS_8BYTE) { in fsl_edma_probe()
580 fsl_edma->dma_dev.src_addr_widths |= BIT(DMA_SLAVE_BUSWIDTH_8_BYTES); in fsl_edma_probe()
581 fsl_edma->dma_dev.dst_addr_widths |= BIT(DMA_SLAVE_BUSWIDTH_8_BYTES); in fsl_edma_probe()
584 fsl_edma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); in fsl_edma_probe()
585 if (drvdata->flags & FSL_EDMA_DRV_DEV_TO_DEV) in fsl_edma_probe()
586 fsl_edma->dma_dev.directions |= BIT(DMA_DEV_TO_DEV); in fsl_edma_probe()
588 fsl_edma->dma_dev.copy_align = drvdata->flags & FSL_EDMA_DRV_ALIGN_64BYTE ? in fsl_edma_probe()
593 dma_set_max_seg_size(fsl_edma->dma_dev.dev, in fsl_edma_probe()
596 fsl_edma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT; in fsl_edma_probe()
600 ret = dma_async_device_register(&fsl_edma->dma_dev); in fsl_edma_probe()
602 dev_err(&pdev->dev, in fsl_edma_probe()
603 "Can't register Freescale eDMA engine. (%d)\n", ret); in fsl_edma_probe()
608 drvdata->flags & FSL_EDMA_DRV_SPLIT_REG ? fsl_edma3_xlate : fsl_edma_xlate, in fsl_edma_probe()
611 dev_err(&pdev->dev, in fsl_edma_probe()
612 "Can't register Freescale eDMA of_dma. (%d)\n", ret); in fsl_edma_probe()
613 dma_async_device_unregister(&fsl_edma->dma_dev); in fsl_edma_probe()
618 if (!(drvdata->flags & FSL_EDMA_DRV_SPLIT_REG)) in fsl_edma_probe()
619 edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr); in fsl_edma_probe()
626 struct device_node *np = pdev->dev.of_node; in fsl_edma_remove()
630 fsl_edma_cleanup_vchan(&fsl_edma->dma_dev); in fsl_edma_remove()
632 dma_async_device_unregister(&fsl_edma->dma_dev); in fsl_edma_remove()
633 fsl_disable_clocks(fsl_edma, fsl_edma->drvdata->dmamuxs); in fsl_edma_remove()
645 for (i = 0; i < fsl_edma->n_chans; i++) { in fsl_edma_suspend_late()
646 fsl_chan = &fsl_edma->chans[i]; in fsl_edma_suspend_late()
647 if (fsl_edma->chan_masked & BIT(i)) in fsl_edma_suspend_late()
649 spin_lock_irqsave(&fsl_chan->vchan.lock, flags); in fsl_edma_suspend_late()
651 if (unlikely(!fsl_chan->idle)) { in fsl_edma_suspend_late()
652 dev_warn(dev, "WARN: There is non-idle channel."); in fsl_edma_suspend_late()
657 fsl_chan->pm_state = SUSPENDED; in fsl_edma_suspend_late()
658 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); in fsl_edma_suspend_late()
668 struct edma_regs *regs = &fsl_edma->regs; in fsl_edma_resume_early()
671 for (i = 0; i < fsl_edma->n_chans; i++) { in fsl_edma_resume_early()
672 fsl_chan = &fsl_edma->chans[i]; in fsl_edma_resume_early()
673 if (fsl_edma->chan_masked & BIT(i)) in fsl_edma_resume_early()
675 fsl_chan->pm_state = RUNNING; in fsl_edma_resume_early()
677 if (fsl_chan->slave_id != 0) in fsl_edma_resume_early()
678 fsl_edma_chan_mux(fsl_chan, fsl_chan->slave_id, true); in fsl_edma_resume_early()
681 if (!(fsl_edma->drvdata->flags & FSL_EDMA_DRV_SPLIT_REG)) in fsl_edma_resume_early()
682 edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr); in fsl_edma_resume_early()
688 * eDMA provides the service to others, so it should be suspend late
689 * and resume early. When eDMA suspend, all of the clients should stop
699 .name = "fsl-edma",
719 MODULE_ALIAS("platform:fsl-edma");
720 MODULE_DESCRIPTION("Freescale eDMA engine driver");