51 #define TOM_OFFSET			0xa0
53 #define TOLUD_OFFSET			0xbc
55 #define CAPID_C_OFFSET			0xec
59 #define CAPID_E_OFFSET			0xf0
63 #define ERRSTS_OFFSET			0xc8
68 #define ERRCMD_OFFSET			0xca
75 #define IBECC_ACTIVATE_EN		BIT(0)
86 #define MCHBAR_OFFSET			0x48
87 #define MCHBAR_EN			BIT_ULL(0)
89 #define MCHBAR_SIZE			0x10000
94 #define MAD_INTER_CHANNEL_DDR_TYPE(v)	GET_BITFIELD(v, 0, 2)
101 #define MAD_INTRA_CH_DIMM_L_MAP(v)	GET_BITFIELD(v, 0, 0)
104 #define MAD_DIMM_CH0_OFFSET		(IMC_BASE + 0xc)
105 #define MAD_DIMM_CH_DIMM_L_SIZE(v)	((u64)GET_BITFIELD(v, 0, 6) << 29)
111 #define MAD_MC_HASH_OFFSET		(IMC_BASE + 0x1b8)
115 #define CHANNEL_HASH_OFFSET		(IMC_BASE + 0x24)
117 #define CHANNEL_EHASH_OFFSET		(IMC_BASE + 0x28)
198 #define DID_EHL_SKU5	0x4514
199 #define DID_EHL_SKU6	0x4528
200 #define DID_EHL_SKU7	0x452a
201 #define DID_EHL_SKU8	0x4516
202 #define DID_EHL_SKU9	0x452c
203 #define DID_EHL_SKU10	0x452e
204 #define DID_EHL_SKU11	0x4532
205 #define DID_EHL_SKU12	0x4518
206 #define DID_EHL_SKU13	0x451a
207 #define DID_EHL_SKU14	0x4534
208 #define DID_EHL_SKU15	0x4536
211 #define DID_ICL_SKU8	0x4581
212 #define DID_ICL_SKU10	0x4585
213 #define DID_ICL_SKU11	0x4589
214 #define DID_ICL_SKU12	0x458d
217 #define DID_TGL_SKU	0x9a14
220 #define DID_ADL_SKU1	0x4601
221 #define DID_ADL_SKU2	0x4602
222 #define DID_ADL_SKU3	0x4621
223 #define DID_ADL_SKU4	0x4641
317 		GET_BITFIELD(eaddr, 0, intlv_bit - 1);  in tgl_err_addr_to_mem_addr()
356 		   GET_BITFIELD(eaddr, 0, intlv_bit - 1);  in adl_err_addr_to_imc_addr()
363 	.imc_base		= 0x5000,
364 	.ibecc_base		= 0xdc00,
366 	.ibecc_error_log_offset	= 0x170,
373 	.imc_base		= 0x5000,
374 	.ibecc_base		= 0xd800,
375 	.ibecc_error_log_offset	= 0x170,
384 	.imc_base		= 0x5000,
385 	.cmf_base		= 0x11000,
386 	.cmf_size		= 0x800,
387 	.ms_hash_offset		= 0xac,
388 	.ibecc_base		= 0xd400,
389 	.ibecc_error_log_offset	= 0x170,
398 	.imc_base		= 0xd800,
399 	.ibecc_base		= 0xd400,
400 	.ibecc_error_log_offset	= 0x68,
437 	case 0:  in get_width()
453 	case 0:  in get_memory_type()
470 	u64 hash_addr = addr & mask, hash = 0;  in decode_chan_idx()
486 	channel_addr |= GET_BITFIELD(addr, 0, intlv_bit - 1);  in decode_channel_addr()
519 		edac_dbg(0, "Address 0x%llx out of range\n", addr);  in igen6_decode()
539 	return 0;  in igen6_decode()
585 	return 0;  in ecclog_gen_pool_add()
605 	return 0;  in ecclog_read_and_clear()
624 	struct igen6_imc *imc = &igen6_pvt->imc[0];  in errcmd_enable_error_reporting()
641 	return 0;  in errcmd_enable_error_reporting()
647 	int i, n = 0;  in ecclog_handler()
650 	for (i = 0; i < res_cfg->num_imc; i++) {  in ecclog_handler()
681 		memset(&res, 0, sizeof(res));  in ecclog_work_cb()
690 		edac_dbg(2, "MC %d, ecclog = 0x%llx\n", node->mc, node->ecclog);  in ecclog_work_cb()
692 		igen6_mc_printk(mci, KERN_DEBUG, "ADDR 0x%llx ", res.sys_addr);  in ecclog_work_cb()
705 	for (i = 0; i < res_cfg->num_imc; i++)  in ecclog_irq_work_cb()
722 	 * doesn't clear the bit NMI_REASON_CLEAR_SERR (in port 0x61) to  in ecclog_nmi_handler()
749 	if ((mce->status & 0xefff) >> 7 != 1)  in ecclog_mce_handler()
757 	edac_dbg(0, "CPU %d: Machine Check %s: 0x%llx Bank %d: 0x%llx\n",  in ecclog_mce_handler()
760 	edac_dbg(0, "TSC 0x%llx\n", mce->tsc);  in ecclog_mce_handler()
761 	edac_dbg(0, "ADDR 0x%llx\n", mce->addr);  in ecclog_mce_handler()
762 	edac_dbg(0, "MISC 0x%llx\n", mce->misc);  in ecclog_mce_handler()
763 	edac_dbg(0, "PROCESSOR %u:0x%x TIME %llu SOCKET %u APIC 0x%x\n",  in ecclog_mce_handler()
812 	for (i = 0; i < NUM_CHANNELS; i++) {  in igen6_get_dimm_config()
821 		ndimms = 0;  in igen6_get_dimm_config()
823 		for (j = 0; j < NUM_DIMMS; j++) {  in igen6_get_dimm_config()
824 			dimm = edac_get_dimm(mci, i, j, 0);  in igen6_get_dimm_config()
827 				dtype = get_width(0, mad_dimm);  in igen6_get_dimm_config()
844 			edac_dbg(0, "MC %d, Channel %d, DIMM %d, Size %llu MiB (%u pages)\n",  in igen6_get_dimm_config()
856 	edac_dbg(0, "MC %d, total size %llu MiB\n", mc, imc->size >> 20);  in igen6_get_dimm_config()
858 	return 0;  in igen6_get_dimm_config()
864 #define TOUUD_OFFSET	0xa8
870 	edac_dbg(2, "CHANNEL_HASH     : 0x%x\n",  in igen6_reg_dump()
872 	edac_dbg(2, "CHANNEL_EHASH    : 0x%x\n",  in igen6_reg_dump()
874 	edac_dbg(2, "MAD_INTER_CHANNEL: 0x%x\n",  in igen6_reg_dump()
876 	edac_dbg(2, "ECC_ERROR_LOG    : 0x%llx\n",  in igen6_reg_dump()
879 	for (i = 0; i < NUM_CHANNELS; i++) {  in igen6_reg_dump()
880 		edac_dbg(2, "MAD_INTRA_CH%d    : 0x%x\n", i,  in igen6_reg_dump()
882 		edac_dbg(2, "MAD_DIMM_CH%d     : 0x%x\n", i,  in igen6_reg_dump()
885 	edac_dbg(2, "TOLUD            : 0x%x", igen6_tolud);  in igen6_reg_dump()
886 	edac_dbg(2, "TOUUD            : 0x%llx", igen6_touud);  in igen6_reg_dump()
887 	edac_dbg(2, "TOM              : 0x%llx", igen6_tom);  in igen6_reg_dump()
897 		edac_dbg(0, "Address 0x%llx out of range\n", val);  in debugfs_u64_set()
898 		return 0;  in debugfs_u64_set()
901 	pr_warn_once("Fake error to 0x%llx injected via debugfs\n", val);  in debugfs_u64_set()
906 	if (!ecclog_gen_pool_add(0, ecclog))  in debugfs_u64_set()
909 	return 0;  in debugfs_u64_set()
998 	return 0;  in igen6_pci_setup()
1016 		igen6_printk(KERN_ERR, "Failed to ioremap 0x%llx\n", mchbar);  in igen6_register_mci()
1020 	layers[0].type = EDAC_MC_LAYER_CHANNEL;  in igen6_register_mci()
1021 	layers[0].size = NUM_CHANNELS;  in igen6_register_mci()
1022 	layers[0].is_virt_csrow = false;  in igen6_register_mci()
1027 	mci = edac_mc_alloc(mc, ARRAY_SIZE(layers), layers, 0);  in igen6_register_mci()
1076 	return 0;  in igen6_register_mci()
1094 	for (i = 0; i < res_cfg->num_imc; i++) {  in igen6_unregister_mcis()
1109 	struct igen6_imc *imc = &igen6_pvt->imc[0];  in igen6_mem_slice_setup()
1119 	if (imc[0].size < imc[1].size) {  in igen6_mem_slice_setup()
1120 		ms_s_size = imc[0].size;  in igen6_mem_slice_setup()
1124 		ms_l_map  = 0;  in igen6_mem_slice_setup()
1130 	edac_dbg(0, "ms_s_size: %llu MiB, ms_l_map %d\n",  in igen6_mem_slice_setup()
1134 		return 0;  in igen6_mem_slice_setup()
1138 		igen6_printk(KERN_ERR, "Failed to ioremap cmf 0x%llx\n", base);  in igen6_mem_slice_setup()
1145 	edac_dbg(0, "MEM_SLICE_HASH: 0x%llx\n", ms_hash);  in igen6_mem_slice_setup()
1149 	return 0;  in igen6_mem_slice_setup()
1158 		return 0;  in register_err_handler()
1162 				  0, IGEN6_NMI_NAME);  in register_err_handler()
1168 	return 0;  in register_err_handler()
1198 	for (i = 0; i < res_cfg->num_imc; i++) {  in igen6_probe()
1234 	return 0;  in igen6_probe()
1289 	return 0;  in igen6_init()