Lines Matching +full:level +full:- +full:detect
1 // SPDX-License-Identifier: GPL-2.0-only
21 #include <linux/pinctrl/pinconf-generic.h>
28 #include "gpio-tangier.h"
31 #define GPLR 0x004 /* Pin level r/o */
35 #define GRER 0x064 /* Rising edge detect */
36 #define GFER 0x07c /* Falling edge detect */
41 #define GLPR 0x318 /* Level input polarity */
44 * struct tng_gpio_context - Context to be saved during suspend-resume
45 * @level: Pin level
47 * @grer: Rising edge detect enable
48 * @gfer: Falling edge detect enable
53 u32 level; member
67 return priv->reg_base + reg + reg_offset * 4; in gpio_reg()
78 return priv->reg_base + reg + reg_offset * 4; in gpio_reg_and_bit()
100 raw_spin_lock_irqsave(&priv->lock, flags); in tng_gpio_set()
104 raw_spin_unlock_irqrestore(&priv->lock, flags); in tng_gpio_set()
117 raw_spin_lock_irqsave(&priv->lock, flags); in tng_gpio_direction_input()
123 raw_spin_unlock_irqrestore(&priv->lock, flags); in tng_gpio_direction_input()
139 raw_spin_lock_irqsave(&priv->lock, flags); in tng_gpio_direction_output()
145 raw_spin_unlock_irqrestore(&priv->lock, flags); in tng_gpio_direction_output()
174 raw_spin_lock_irqsave(&priv->lock, flags); in tng_gpio_set_debounce()
183 raw_spin_unlock_irqrestore(&priv->lock, flags); in tng_gpio_set_debounce()
202 return -ENOTSUPP; in tng_gpio_set_config()
214 gisr = gpio_reg_and_bit(&priv->chip, gpio, GISR, &shift); in tng_irq_ack()
216 raw_spin_lock_irqsave(&priv->lock, flags); in tng_irq_ack()
218 raw_spin_unlock_irqrestore(&priv->lock, flags); in tng_irq_ack()
228 gimr = gpio_reg_and_bit(&priv->chip, gpio, GIMR, &shift); in tng_irq_unmask_mask()
230 raw_spin_lock_irqsave(&priv->lock, flags); in tng_irq_unmask_mask()
239 raw_spin_unlock_irqrestore(&priv->lock, flags); in tng_irq_unmask_mask()
248 gpiochip_disable_irq(&priv->chip, gpio); in tng_irq_mask()
256 gpiochip_enable_irq(&priv->chip, gpio); in tng_irq_unmask()
265 void __iomem *grer = gpio_reg(&priv->chip, gpio, GRER); in tng_irq_set_type()
266 void __iomem *gfer = gpio_reg(&priv->chip, gpio, GFER); in tng_irq_set_type()
267 void __iomem *gitr = gpio_reg(&priv->chip, gpio, GITR); in tng_irq_set_type()
268 void __iomem *glpr = gpio_reg(&priv->chip, gpio, GLPR); in tng_irq_set_type()
273 raw_spin_lock_irqsave(&priv->lock, flags); in tng_irq_set_type()
290 * To prevent glitches from triggering an unintended level interrupt, in tng_irq_set_type()
314 raw_spin_unlock_irqrestore(&priv->lock, flags); in tng_irq_set_type()
324 void __iomem *gwmr = gpio_reg(&priv->chip, gpio, priv->wake_regs.gwmr); in tng_irq_set_wake()
325 void __iomem *gwsr = gpio_reg(&priv->chip, gpio, priv->wake_regs.gwsr); in tng_irq_set_wake()
330 raw_spin_lock_irqsave(&priv->lock, flags); in tng_irq_set_wake()
342 raw_spin_unlock_irqrestore(&priv->lock, flags); in tng_irq_set_wake()
344 dev_dbg(priv->dev, "%s wake for gpio %lu\n", str_enable_disable(on), gpio); in tng_irq_set_wake()
349 .name = "gpio-tangier",
369 for (base = 0; base < priv->chip.ngpio; base += 32) { in tng_irq_handler()
370 void __iomem *gisr = gpio_reg(&priv->chip, base, GISR); in tng_irq_handler()
371 void __iomem *gimr = gpio_reg(&priv->chip, base, GIMR); in tng_irq_handler()
381 generic_handle_domain_irq(gc->irq.domain, base + gpio); in tng_irq_handler()
393 for (base = 0; base < priv->chip.ngpio; base += 32) { in tng_irq_init_hw()
394 /* Clear the rising-edge detect register */ in tng_irq_init_hw()
395 reg = gpio_reg(&priv->chip, base, GRER); in tng_irq_init_hw()
398 /* Clear the falling-edge detect register */ in tng_irq_init_hw()
399 reg = gpio_reg(&priv->chip, base, GFER); in tng_irq_init_hw()
413 for (i = 0; i < priv->pin_info.nranges; i++) { in tng_gpio_add_pin_ranges()
414 range = &priv->pin_info.pin_ranges[i]; in tng_gpio_add_pin_ranges()
415 ret = gpiochip_add_pin_range(&priv->chip, in tng_gpio_add_pin_ranges()
416 priv->pin_info.name, in tng_gpio_add_pin_ranges()
417 range->gpio_base, in tng_gpio_add_pin_ranges()
418 range->pin_base, in tng_gpio_add_pin_ranges()
419 range->npins); in tng_gpio_add_pin_ranges()
421 dev_err(priv->dev, "failed to add GPIO pin range\n"); in tng_gpio_add_pin_ranges()
431 const struct tng_gpio_info *info = &gpio->info; in devm_tng_gpio_probe()
432 size_t nctx = DIV_ROUND_UP(info->ngpio, 32); in devm_tng_gpio_probe()
436 gpio->ctx = devm_kcalloc(dev, nctx, sizeof(*gpio->ctx), GFP_KERNEL); in devm_tng_gpio_probe()
437 if (!gpio->ctx) in devm_tng_gpio_probe()
438 return -ENOMEM; in devm_tng_gpio_probe()
440 gpio->chip.label = dev_name(dev); in devm_tng_gpio_probe()
441 gpio->chip.parent = dev; in devm_tng_gpio_probe()
442 gpio->chip.request = gpiochip_generic_request; in devm_tng_gpio_probe()
443 gpio->chip.free = gpiochip_generic_free; in devm_tng_gpio_probe()
444 gpio->chip.direction_input = tng_gpio_direction_input; in devm_tng_gpio_probe()
445 gpio->chip.direction_output = tng_gpio_direction_output; in devm_tng_gpio_probe()
446 gpio->chip.get = tng_gpio_get; in devm_tng_gpio_probe()
447 gpio->chip.set = tng_gpio_set; in devm_tng_gpio_probe()
448 gpio->chip.get_direction = tng_gpio_get_direction; in devm_tng_gpio_probe()
449 gpio->chip.set_config = tng_gpio_set_config; in devm_tng_gpio_probe()
450 gpio->chip.base = info->base; in devm_tng_gpio_probe()
451 gpio->chip.ngpio = info->ngpio; in devm_tng_gpio_probe()
452 gpio->chip.can_sleep = false; in devm_tng_gpio_probe()
453 gpio->chip.add_pin_ranges = tng_gpio_add_pin_ranges; in devm_tng_gpio_probe()
455 raw_spin_lock_init(&gpio->lock); in devm_tng_gpio_probe()
457 girq = &gpio->chip.irq; in devm_tng_gpio_probe()
459 girq->init_hw = tng_irq_init_hw; in devm_tng_gpio_probe()
460 girq->parent_handler = tng_irq_handler; in devm_tng_gpio_probe()
461 girq->num_parents = 1; in devm_tng_gpio_probe()
462 girq->parents = devm_kcalloc(dev, girq->num_parents, in devm_tng_gpio_probe()
463 sizeof(*girq->parents), GFP_KERNEL); in devm_tng_gpio_probe()
464 if (!girq->parents) in devm_tng_gpio_probe()
465 return -ENOMEM; in devm_tng_gpio_probe()
467 girq->parents[0] = gpio->irq; in devm_tng_gpio_probe()
468 girq->first = info->first; in devm_tng_gpio_probe()
469 girq->default_type = IRQ_TYPE_NONE; in devm_tng_gpio_probe()
470 girq->handler = handle_bad_irq; in devm_tng_gpio_probe()
472 ret = devm_gpiochip_add_data(dev, &gpio->chip, gpio); in devm_tng_gpio_probe()
483 struct tng_gpio_context *ctx = priv->ctx; in tng_gpio_suspend()
487 raw_spin_lock_irqsave(&priv->lock, flags); in tng_gpio_suspend()
489 for (base = 0; base < priv->chip.ngpio; base += 32, ctx++) { in tng_gpio_suspend()
491 ctx->level = readl(gpio_reg(&priv->chip, base, GPLR)); in tng_gpio_suspend()
493 ctx->gpdr = readl(gpio_reg(&priv->chip, base, GPDR)); in tng_gpio_suspend()
494 ctx->grer = readl(gpio_reg(&priv->chip, base, GRER)); in tng_gpio_suspend()
495 ctx->gfer = readl(gpio_reg(&priv->chip, base, GFER)); in tng_gpio_suspend()
496 ctx->gimr = readl(gpio_reg(&priv->chip, base, GIMR)); in tng_gpio_suspend()
498 ctx->gwmr = readl(gpio_reg(&priv->chip, base, priv->wake_regs.gwmr)); in tng_gpio_suspend()
501 raw_spin_unlock_irqrestore(&priv->lock, flags); in tng_gpio_suspend()
510 struct tng_gpio_context *ctx = priv->ctx; in tng_gpio_resume()
514 raw_spin_lock_irqsave(&priv->lock, flags); in tng_gpio_resume()
516 for (base = 0; base < priv->chip.ngpio; base += 32, ctx++) { in tng_gpio_resume()
518 writel(ctx->level, gpio_reg(&priv->chip, base, GPSR)); in tng_gpio_resume()
520 writel(ctx->gpdr, gpio_reg(&priv->chip, base, GPDR)); in tng_gpio_resume()
521 writel(ctx->grer, gpio_reg(&priv->chip, base, GRER)); in tng_gpio_resume()
522 writel(ctx->gfer, gpio_reg(&priv->chip, base, GFER)); in tng_gpio_resume()
523 writel(ctx->gimr, gpio_reg(&priv->chip, base, GIMR)); in tng_gpio_resume()
525 writel(ctx->gwmr, gpio_reg(&priv->chip, base, priv->wake_regs.gwmr)); in tng_gpio_resume()
528 raw_spin_unlock_irqrestore(&priv->lock, flags); in tng_gpio_resume()