Lines Matching +full:0 +full:x44
21 #define DSI_CMD2BKX_SEL 0xFF
22 #define DSI_CMD1 0
24 #define DSI_CMD2BK_MASK GENMASK(3, 0)
27 #define DSI_CMD2_BK0_PVGAMCTRL 0xB0 /* Positive Voltage Gamma Control */
28 #define DSI_CMD2_BK0_NVGAMCTRL 0xB1 /* Negative Voltage Gamma Control */
29 #define DSI_CMD2_BK0_LNESET 0xC0 /* Display Line setting */
30 #define DSI_CMD2_BK0_PORCTRL 0xC1 /* Porch control */
31 #define DSI_CMD2_BK0_INVSEL 0xC2 /* Inversion selection, Frame Rate Control */
34 #define DSI_CMD2_BK1_VRHS 0xB0 /* Vop amplitude setting */
35 #define DSI_CMD2_BK1_VCOM 0xB1 /* VCOM amplitude setting */
36 #define DSI_CMD2_BK1_VGHSS 0xB2 /* VGH Voltage setting */
37 #define DSI_CMD2_BK1_TESTCMD 0xB3 /* TEST Command Setting */
38 #define DSI_CMD2_BK1_VGLS 0xB5 /* VGL Voltage setting */
39 #define DSI_CMD2_BK1_PWCTLR1 0xB7 /* Power Control 1 */
40 #define DSI_CMD2_BK1_PWCTLR2 0xB8 /* Power Control 2 */
41 #define DSI_CMD2_BK1_SPD1 0xC1 /* Source pre_drive timing set1 */
42 #define DSI_CMD2_BK1_SPD2 0xC2 /* Source EQ2 Setting */
43 #define DSI_CMD2_BK1_MIPISET1 0xD0 /* MIPI Setting 1 */
47 #define DSI_CMD2_BK0_GAMCTRL_VC0_MASK GENMASK(3, 0)
48 #define DSI_CMD2_BK0_GAMCTRL_VC4_MASK GENMASK(5, 0)
49 #define DSI_CMD2_BK0_GAMCTRL_VC8_MASK GENMASK(5, 0)
50 #define DSI_CMD2_BK0_GAMCTRL_VC16_MASK GENMASK(4, 0)
51 #define DSI_CMD2_BK0_GAMCTRL_VC24_MASK GENMASK(4, 0)
52 #define DSI_CMD2_BK0_GAMCTRL_VC52_MASK GENMASK(3, 0)
53 #define DSI_CMD2_BK0_GAMCTRL_VC80_MASK GENMASK(5, 0)
54 #define DSI_CMD2_BK0_GAMCTRL_VC108_MASK GENMASK(3, 0)
55 #define DSI_CMD2_BK0_GAMCTRL_VC147_MASK GENMASK(3, 0)
56 #define DSI_CMD2_BK0_GAMCTRL_VC175_MASK GENMASK(5, 0)
57 #define DSI_CMD2_BK0_GAMCTRL_VC203_MASK GENMASK(3, 0)
58 #define DSI_CMD2_BK0_GAMCTRL_VC231_MASK GENMASK(4, 0)
59 #define DSI_CMD2_BK0_GAMCTRL_VC239_MASK GENMASK(4, 0)
60 #define DSI_CMD2_BK0_GAMCTRL_VC247_MASK GENMASK(5, 0)
61 #define DSI_CMD2_BK0_GAMCTRL_VC251_MASK GENMASK(5, 0)
62 #define DSI_CMD2_BK0_GAMCTRL_VC255_MASK GENMASK(4, 0)
63 #define DSI_CMD2_BK0_LNESET_LINE_MASK GENMASK(6, 0)
65 #define DSI_CMD2_BK0_LNESET_LINEDELTA GENMASK(1, 0)
66 #define DSI_CMD2_BK0_PORCTRL_VBP_MASK GENMASK(7, 0)
67 #define DSI_CMD2_BK0_PORCTRL_VFP_MASK GENMASK(7, 0)
69 #define DSI_CMD2_BK0_INVSEL_NLINV_MASK GENMASK(2, 0)
70 #define DSI_CMD2_BK0_INVSEL_RTNI_MASK GENMASK(4, 0)
73 #define DSI_CMD2_BK1_VRHA_MASK GENMASK(7, 0)
74 #define DSI_CMD2_BK1_VCOM_MASK GENMASK(7, 0)
75 #define DSI_CMD2_BK1_VGHSS_MASK GENMASK(3, 0)
78 #define DSI_CMD2_BK1_VGLS_MASK GENMASK(3, 0)
81 #define DSI_CMD2_BK1_PWRCTRL1_APOS_MASK GENMASK(1, 0)
83 #define DSI_CMD2_BK1_PWRCTRL2_AVCL_MASK GENMASK(1, 0)
85 #define DSI_CMD2_BK1_SPD1_T2D_MASK GENMASK(3, 0)
87 #define DSI_CMD2_BK1_SPD2_T3D_MASK GENMASK(3, 0)
95 OP_BIAS_OFF = 0,
165 { -7060, 0x0 }, { -7470, 0x1 }, in st7701_vgls_map()
166 { -7910, 0x2 }, { -8140, 0x3 }, in st7701_vgls_map()
167 { -8650, 0x4 }, { -8920, 0x5 }, in st7701_vgls_map()
168 { -9210, 0x6 }, { -9510, 0x7 }, in st7701_vgls_map()
169 { -9830, 0x8 }, { -10170, 0x9 }, in st7701_vgls_map()
170 { -10530, 0xa }, { -10910, 0xb }, in st7701_vgls_map()
171 { -11310, 0xc }, { -11730, 0xd }, in st7701_vgls_map()
172 { -12200, 0xe }, { -12690, 0xf } in st7701_vgls_map()
176 for (i = 0; i < ARRAY_SIZE(map); i++) in st7701_vgls_map()
180 return 0; in st7701_vgls_map()
192 ST7701_DSI(st7701, DSI_CMD2BKX_SEL, 0x77, 0x01, 0x00, 0x00, val); in st7701_switch_cmd_bkx()
202 ST7701_DSI(st7701, MIPI_DCS_SOFT_RESET, 0x00); in st7701_init_sequence()
207 ST7701_DSI(st7701, MIPI_DCS_EXIT_SLEEP_MODE, 0x00); in st7701_init_sequence()
212 st7701_switch_cmd_bkx(st7701, true, 0); in st7701_init_sequence()
220 * Line[6:0]: select number of vertical lines of the TFT matrix in in st7701_init_sequence()
223 * Line_delta[1:0]: add 0/2/4/6 extra lines to line count selected in st7701_init_sequence()
224 * using Line[6:0] in st7701_init_sequence()
227 * LN = ((Line[6:0] + 1) * 8) + (LDE_EN ? Line_delta[1:0] * 2 : 0) in st7701_init_sequence()
231 (linecountrem2 ? DSI_CMD2_BK0_LNESET_LDE_EN : 0), in st7701_init_sequence()
240 * PCLK = 512 + (RTNI[4:0] * 16) in st7701_init_sequence()
253 /* Vop = 3.5375V + (VRHA[7:0] * 0.0125V) */ in st7701_init_sequence()
258 /* Vcom = 0.1V + (VCOM[7:0] * 0.0125V) */ in st7701_init_sequence()
263 /* Vgh = 11.5V + (VGHSS[7:0] * 0.5V) */ in st7701_init_sequence()
286 /* Avdd = 6.2V + (AVDD[1:0] * 0.2V) , Avcl = -4.4V - (AVCL[1:0] * 0.2V) */ in st7701_init_sequence()
293 /* T2D = 0.2us * T2D[3:0] */ in st7701_init_sequence()
299 /* T3D = 4us + (0.8us * T3D[3:0]) */ in st7701_init_sequence()
307 (desc->eot_en ? DSI_CMD2_BK1_MIPISET1_EOT_EN : 0)); in st7701_init_sequence()
316 ST7701_DSI(st7701, 0xE0, 0x00, 0x00, 0x02); in ts8550b_gip_sequence()
317 ST7701_DSI(st7701, 0xE1, 0x0B, 0x00, 0x0D, 0x00, 0x0C, 0x00, 0x0E, in ts8550b_gip_sequence()
318 0x00, 0x00, 0x44, 0x44); in ts8550b_gip_sequence()
319 ST7701_DSI(st7701, 0xE2, 0x33, 0x33, 0x44, 0x44, 0x64, 0x00, 0x66, in ts8550b_gip_sequence()
320 0x00, 0x65, 0x00, 0x67, 0x00, 0x00); in ts8550b_gip_sequence()
321 ST7701_DSI(st7701, 0xE3, 0x00, 0x00, 0x33, 0x33); in ts8550b_gip_sequence()
322 ST7701_DSI(st7701, 0xE4, 0x44, 0x44); in ts8550b_gip_sequence()
323 ST7701_DSI(st7701, 0xE5, 0x0C, 0x78, 0x3C, 0xA0, 0x0E, 0x78, 0x3C, in ts8550b_gip_sequence()
324 0xA0, 0x10, 0x78, 0x3C, 0xA0, 0x12, 0x78, 0x3C, 0xA0); in ts8550b_gip_sequence()
325 ST7701_DSI(st7701, 0xE6, 0x00, 0x00, 0x33, 0x33); in ts8550b_gip_sequence()
326 ST7701_DSI(st7701, 0xE7, 0x44, 0x44); in ts8550b_gip_sequence()
327 ST7701_DSI(st7701, 0xE8, 0x0D, 0x78, 0x3C, 0xA0, 0x0F, 0x78, 0x3C, in ts8550b_gip_sequence()
328 0xA0, 0x11, 0x78, 0x3C, 0xA0, 0x13, 0x78, 0x3C, 0xA0); in ts8550b_gip_sequence()
329 ST7701_DSI(st7701, 0xEB, 0x02, 0x02, 0x39, 0x39, 0xEE, 0x44, 0x00); in ts8550b_gip_sequence()
330 ST7701_DSI(st7701, 0xEC, 0x00, 0x00); in ts8550b_gip_sequence()
331 ST7701_DSI(st7701, 0xED, 0xFF, 0xF1, 0x04, 0x56, 0x72, 0x3F, 0xFF, in ts8550b_gip_sequence()
332 0xFF, 0xFF, 0xFF, 0xF3, 0x27, 0x65, 0x40, 0x1F, 0xFF); in ts8550b_gip_sequence()
337 ST7701_DSI(st7701, 0xEE, 0x42); in dmt028vghmcmi_1a_gip_sequence()
338 ST7701_DSI(st7701, 0xE0, 0x00, 0x00, 0x02); in dmt028vghmcmi_1a_gip_sequence()
340 ST7701_DSI(st7701, 0xE1, in dmt028vghmcmi_1a_gip_sequence()
341 0x04, 0xA0, 0x06, 0xA0, in dmt028vghmcmi_1a_gip_sequence()
342 0x05, 0xA0, 0x07, 0xA0, in dmt028vghmcmi_1a_gip_sequence()
343 0x00, 0x44, 0x44); in dmt028vghmcmi_1a_gip_sequence()
344 ST7701_DSI(st7701, 0xE2, in dmt028vghmcmi_1a_gip_sequence()
345 0x00, 0x00, 0x00, 0x00, in dmt028vghmcmi_1a_gip_sequence()
346 0x00, 0x00, 0x00, 0x00, in dmt028vghmcmi_1a_gip_sequence()
347 0x00, 0x00, 0x00, 0x00); in dmt028vghmcmi_1a_gip_sequence()
348 ST7701_DSI(st7701, 0xE3, in dmt028vghmcmi_1a_gip_sequence()
349 0x00, 0x00, 0x22, 0x22); in dmt028vghmcmi_1a_gip_sequence()
350 ST7701_DSI(st7701, 0xE4, 0x44, 0x44); in dmt028vghmcmi_1a_gip_sequence()
351 ST7701_DSI(st7701, 0xE5, in dmt028vghmcmi_1a_gip_sequence()
352 0x0C, 0x90, 0xA0, 0xA0, in dmt028vghmcmi_1a_gip_sequence()
353 0x0E, 0x92, 0xA0, 0xA0, in dmt028vghmcmi_1a_gip_sequence()
354 0x08, 0x8C, 0xA0, 0xA0, in dmt028vghmcmi_1a_gip_sequence()
355 0x0A, 0x8E, 0xA0, 0xA0); in dmt028vghmcmi_1a_gip_sequence()
356 ST7701_DSI(st7701, 0xE6, in dmt028vghmcmi_1a_gip_sequence()
357 0x00, 0x00, 0x22, 0x22); in dmt028vghmcmi_1a_gip_sequence()
358 ST7701_DSI(st7701, 0xE7, 0x44, 0x44); in dmt028vghmcmi_1a_gip_sequence()
359 ST7701_DSI(st7701, 0xE8, in dmt028vghmcmi_1a_gip_sequence()
360 0x0D, 0x91, 0xA0, 0xA0, in dmt028vghmcmi_1a_gip_sequence()
361 0x0F, 0x93, 0xA0, 0xA0, in dmt028vghmcmi_1a_gip_sequence()
362 0x09, 0x8D, 0xA0, 0xA0, in dmt028vghmcmi_1a_gip_sequence()
363 0x0B, 0x8F, 0xA0, 0xA0); in dmt028vghmcmi_1a_gip_sequence()
364 ST7701_DSI(st7701, 0xEB, in dmt028vghmcmi_1a_gip_sequence()
365 0x00, 0x00, 0xE4, 0xE4, in dmt028vghmcmi_1a_gip_sequence()
366 0x44, 0x00, 0x00); in dmt028vghmcmi_1a_gip_sequence()
367 ST7701_DSI(st7701, 0xED, in dmt028vghmcmi_1a_gip_sequence()
368 0xFF, 0xF5, 0x47, 0x6F, in dmt028vghmcmi_1a_gip_sequence()
369 0x0B, 0xA1, 0xAB, 0xFF, in dmt028vghmcmi_1a_gip_sequence()
370 0xFF, 0xBA, 0x1A, 0xB0, in dmt028vghmcmi_1a_gip_sequence()
371 0xF6, 0x74, 0x5F, 0xFF); in dmt028vghmcmi_1a_gip_sequence()
372 ST7701_DSI(st7701, 0xEF, in dmt028vghmcmi_1a_gip_sequence()
373 0x08, 0x08, 0x08, 0x40, in dmt028vghmcmi_1a_gip_sequence()
374 0x3F, 0x64); in dmt028vghmcmi_1a_gip_sequence()
376 st7701_switch_cmd_bkx(st7701, false, 0); in dmt028vghmcmi_1a_gip_sequence()
379 ST7701_DSI(st7701, 0xE6, 0x7C); in dmt028vghmcmi_1a_gip_sequence()
380 ST7701_DSI(st7701, 0xE8, 0x00, 0x0E); in dmt028vghmcmi_1a_gip_sequence()
382 st7701_switch_cmd_bkx(st7701, false, 0); in dmt028vghmcmi_1a_gip_sequence()
383 ST7701_DSI(st7701, 0x11); in dmt028vghmcmi_1a_gip_sequence()
387 ST7701_DSI(st7701, 0xE8, 0x00, 0x0C); in dmt028vghmcmi_1a_gip_sequence()
389 ST7701_DSI(st7701, 0xE8, 0x00, 0x00); in dmt028vghmcmi_1a_gip_sequence()
391 st7701_switch_cmd_bkx(st7701, false, 0); in dmt028vghmcmi_1a_gip_sequence()
392 ST7701_DSI(st7701, 0x11); in dmt028vghmcmi_1a_gip_sequence()
394 ST7701_DSI(st7701, 0xE8, 0x00, 0x00); in dmt028vghmcmi_1a_gip_sequence()
396 st7701_switch_cmd_bkx(st7701, false, 0); in dmt028vghmcmi_1a_gip_sequence()
398 ST7701_DSI(st7701, 0x3A, 0x70); in dmt028vghmcmi_1a_gip_sequence()
407 ST7701_DSI(st7701, 0xE0, 0x00, 0x00, 0x02); in kd50t048a_gip_sequence()
408 ST7701_DSI(st7701, 0xE1, 0x08, 0x00, 0x0A, 0x00, 0x07, 0x00, 0x09, in kd50t048a_gip_sequence()
409 0x00, 0x00, 0x33, 0x33); in kd50t048a_gip_sequence()
410 ST7701_DSI(st7701, 0xE2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, in kd50t048a_gip_sequence()
411 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); in kd50t048a_gip_sequence()
412 ST7701_DSI(st7701, 0xE3, 0x00, 0x00, 0x33, 0x33); in kd50t048a_gip_sequence()
413 ST7701_DSI(st7701, 0xE4, 0x44, 0x44); in kd50t048a_gip_sequence()
414 ST7701_DSI(st7701, 0xE5, 0x0E, 0x60, 0xA0, 0xA0, 0x10, 0x60, 0xA0, in kd50t048a_gip_sequence()
415 0xA0, 0x0A, 0x60, 0xA0, 0xA0, 0x0C, 0x60, 0xA0, 0xA0); in kd50t048a_gip_sequence()
416 ST7701_DSI(st7701, 0xE6, 0x00, 0x00, 0x33, 0x33); in kd50t048a_gip_sequence()
417 ST7701_DSI(st7701, 0xE7, 0x44, 0x44); in kd50t048a_gip_sequence()
418 ST7701_DSI(st7701, 0xE8, 0x0D, 0x60, 0xA0, 0xA0, 0x0F, 0x60, 0xA0, in kd50t048a_gip_sequence()
419 0xA0, 0x09, 0x60, 0xA0, 0xA0, 0x0B, 0x60, 0xA0, 0xA0); in kd50t048a_gip_sequence()
420 ST7701_DSI(st7701, 0xEB, 0x02, 0x01, 0xE4, 0xE4, 0x44, 0x00, 0x40); in kd50t048a_gip_sequence()
421 ST7701_DSI(st7701, 0xEC, 0x02, 0x01); in kd50t048a_gip_sequence()
422 ST7701_DSI(st7701, 0xED, 0xAB, 0x89, 0x76, 0x54, 0x01, 0xFF, 0xFF, in kd50t048a_gip_sequence()
423 0xFF, 0xFF, 0xFF, 0xFF, 0x10, 0x45, 0x67, 0x98, 0xBA); in kd50t048a_gip_sequence()
431 gpiod_set_value(st7701->reset, 0); in st7701_prepare()
435 if (ret < 0) in st7701_prepare()
448 st7701_switch_cmd_bkx(st7701, false, 0); in st7701_prepare()
450 return 0; in st7701_prepare()
457 ST7701_DSI(st7701, MIPI_DCS_SET_DISPLAY_ON, 0x00); in st7701_enable()
459 return 0; in st7701_enable()
466 ST7701_DSI(st7701, MIPI_DCS_SET_DISPLAY_OFF, 0x00); in st7701_disable()
468 return 0; in st7701_disable()
475 ST7701_DSI(st7701, MIPI_DCS_ENTER_SLEEP_MODE, 0x00); in st7701_unprepare()
479 gpiod_set_value(st7701->reset, 0); in st7701_unprepare()
494 return 0; in st7701_unprepare()
569 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
570 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC0_MASK, 0),
571 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
572 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC4_MASK, 0xe),
573 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
574 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC8_MASK, 0x15),
575 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC16_MASK, 0xf),
577 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
578 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC24_MASK, 0x11),
579 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC52_MASK, 0x8),
580 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC80_MASK, 0x8),
581 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8),
583 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC147_MASK, 0x8),
584 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC175_MASK, 0x23),
585 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC203_MASK, 0x4),
586 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
587 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC231_MASK, 0x13),
589 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC239_MASK, 0x12),
590 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
591 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC247_MASK, 0x2b),
592 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
593 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC251_MASK, 0x34),
594 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
595 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f)
598 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
599 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC0_MASK, 0),
600 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
601 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC4_MASK, 0xe),
602 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0x2) |
603 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC8_MASK, 0x15),
604 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC16_MASK, 0xf),
606 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
607 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC24_MASK, 0x13),
608 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC52_MASK, 0x7),
609 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC80_MASK, 0x9),
610 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8),
612 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC147_MASK, 0x8),
613 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC175_MASK, 0x22),
614 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC203_MASK, 0x4),
615 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
616 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC231_MASK, 0x10),
618 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC239_MASK, 0xe),
619 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
620 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC247_MASK, 0x2c),
621 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
622 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC251_MASK, 0x34),
623 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
624 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f)
670 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
671 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC0_MASK, 0),
672 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
673 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC4_MASK, 0x10),
674 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
675 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC8_MASK, 0x17),
676 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC16_MASK, 0xd),
678 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
679 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC24_MASK, 0x11),
680 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC52_MASK, 0x6),
681 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC80_MASK, 0x5),
682 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8),
684 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC147_MASK, 0x7),
685 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC175_MASK, 0x1f),
686 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC203_MASK, 0x4),
687 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
688 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC231_MASK, 0x11),
690 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC239_MASK, 0xe),
691 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
692 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC247_MASK, 0x29),
693 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
694 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC251_MASK, 0x30),
695 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
696 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f)
699 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
700 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC0_MASK, 0),
701 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
702 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC4_MASK, 0xd),
703 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
704 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC8_MASK, 0x14),
705 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC16_MASK, 0xe),
707 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
708 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC24_MASK, 0x11),
709 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC52_MASK, 0x6),
710 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC80_MASK, 0x4),
711 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8),
713 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC147_MASK, 0x8),
714 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC175_MASK, 0x20),
715 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC203_MASK, 0x5),
716 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
717 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC231_MASK, 0x13),
719 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC239_MASK, 0x13),
720 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
721 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC247_MASK, 0x26),
722 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
723 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC251_MASK, 0x30),
724 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
725 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f)
766 .panel_sleep_delay = 0,
769 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
770 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC0_MASK, 0),
771 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
772 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC4_MASK, 0xd),
773 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
774 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC8_MASK, 0x14),
775 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC16_MASK, 0xd),
777 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
778 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC24_MASK, 0x10),
779 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC52_MASK, 0x5),
780 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC80_MASK, 0x2),
781 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8),
783 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC147_MASK, 0x8),
784 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC175_MASK, 0x1e),
785 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC203_MASK, 0x5),
786 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
787 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC231_MASK, 0x13),
789 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC239_MASK, 0x11),
791 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC247_MASK, 0x23),
792 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
793 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC251_MASK, 0x29),
794 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
795 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC255_MASK, 0x18)
798 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
799 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC0_MASK, 0),
800 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
801 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC4_MASK, 0xc),
802 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
803 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC8_MASK, 0x14),
804 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC16_MASK, 0xc),
806 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
807 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC24_MASK, 0x10),
808 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC52_MASK, 0x5),
809 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC80_MASK, 0x3),
810 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8),
812 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC147_MASK, 0x7),
813 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC175_MASK, 0x20),
814 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC203_MASK, 0x5),
815 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
816 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC231_MASK, 0x13),
818 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC239_MASK, 0x11),
820 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC247_MASK, 0x24),
821 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
822 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC251_MASK, 0x29),
823 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
824 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC255_MASK, 0x18)
858 st7701->supplies[0].supply = "VCC"; in st7701_dsi_probe()
863 if (ret < 0) in st7701_dsi_probe()
873 if (ret < 0) in st7701_dsi_probe()
904 return 0; in st7701_dsi_probe()