Lines Matching full:dispc
360 static void dispc_write(struct dispc_device *dispc, u16 reg, u32 val) in dispc_write() argument
362 iowrite32(val, dispc->base_common + reg); in dispc_write()
365 static u32 dispc_read(struct dispc_device *dispc, u16 reg) in dispc_read() argument
367 return ioread32(dispc->base_common + reg); in dispc_read()
371 void dispc_vid_write(struct dispc_device *dispc, u32 hw_plane, u16 reg, u32 val) in dispc_vid_write() argument
373 void __iomem *base = dispc->base_vid[hw_plane]; in dispc_vid_write()
378 static u32 dispc_vid_read(struct dispc_device *dispc, u32 hw_plane, u16 reg) in dispc_vid_read() argument
380 void __iomem *base = dispc->base_vid[hw_plane]; in dispc_vid_read()
385 static void dispc_ovr_write(struct dispc_device *dispc, u32 hw_videoport, in dispc_ovr_write() argument
388 void __iomem *base = dispc->base_ovr[hw_videoport]; in dispc_ovr_write()
393 static u32 dispc_ovr_read(struct dispc_device *dispc, u32 hw_videoport, u16 reg) in dispc_ovr_read() argument
395 void __iomem *base = dispc->base_ovr[hw_videoport]; in dispc_ovr_read()
400 static void dispc_vp_write(struct dispc_device *dispc, u32 hw_videoport, in dispc_vp_write() argument
403 void __iomem *base = dispc->base_vp[hw_videoport]; in dispc_vp_write()
408 static u32 dispc_vp_read(struct dispc_device *dispc, u32 hw_videoport, u16 reg) in dispc_vp_read() argument
410 void __iomem *base = dispc->base_vp[hw_videoport]; in dispc_vp_read()
440 static u32 REG_GET(struct dispc_device *dispc, u32 idx, u32 start, u32 end) in REG_GET() argument
442 return FLD_GET(dispc_read(dispc, idx), start, end); in REG_GET()
445 static void REG_FLD_MOD(struct dispc_device *dispc, u32 idx, u32 val, in REG_FLD_MOD() argument
448 dispc_write(dispc, idx, FLD_MOD(dispc_read(dispc, idx), val, in REG_FLD_MOD()
452 static u32 VID_REG_GET(struct dispc_device *dispc, u32 hw_plane, u32 idx, in VID_REG_GET() argument
455 return FLD_GET(dispc_vid_read(dispc, hw_plane, idx), start, end); in VID_REG_GET()
458 static void VID_REG_FLD_MOD(struct dispc_device *dispc, u32 hw_plane, u32 idx, in VID_REG_FLD_MOD() argument
461 dispc_vid_write(dispc, hw_plane, idx, in VID_REG_FLD_MOD()
462 FLD_MOD(dispc_vid_read(dispc, hw_plane, idx), in VID_REG_FLD_MOD()
466 static u32 VP_REG_GET(struct dispc_device *dispc, u32 vp, u32 idx, in VP_REG_GET() argument
469 return FLD_GET(dispc_vp_read(dispc, vp, idx), start, end); in VP_REG_GET()
472 static void VP_REG_FLD_MOD(struct dispc_device *dispc, u32 vp, u32 idx, u32 val, in VP_REG_FLD_MOD() argument
475 dispc_vp_write(dispc, vp, idx, FLD_MOD(dispc_vp_read(dispc, vp, idx), in VP_REG_FLD_MOD()
480 static u32 OVR_REG_GET(struct dispc_device *dispc, u32 ovr, u32 idx, in OVR_REG_GET() argument
483 return FLD_GET(dispc_ovr_read(dispc, ovr, idx), start, end); in OVR_REG_GET()
486 static void OVR_REG_FLD_MOD(struct dispc_device *dispc, u32 ovr, u32 idx, in OVR_REG_FLD_MOD() argument
489 dispc_ovr_write(dispc, ovr, idx, in OVR_REG_FLD_MOD()
490 FLD_MOD(dispc_ovr_read(dispc, ovr, idx), in OVR_REG_FLD_MOD()
546 static dispc_irq_t dispc_k2g_vp_read_irqstatus(struct dispc_device *dispc, in dispc_k2g_vp_read_irqstatus() argument
549 u32 stat = dispc_vp_read(dispc, hw_videoport, DISPC_VP_K2G_IRQSTATUS); in dispc_k2g_vp_read_irqstatus()
554 static void dispc_k2g_vp_write_irqstatus(struct dispc_device *dispc, in dispc_k2g_vp_write_irqstatus() argument
559 dispc_vp_write(dispc, hw_videoport, DISPC_VP_K2G_IRQSTATUS, stat); in dispc_k2g_vp_write_irqstatus()
562 static dispc_irq_t dispc_k2g_vid_read_irqstatus(struct dispc_device *dispc, in dispc_k2g_vid_read_irqstatus() argument
565 u32 stat = dispc_vid_read(dispc, hw_plane, DISPC_VID_K2G_IRQSTATUS); in dispc_k2g_vid_read_irqstatus()
570 static void dispc_k2g_vid_write_irqstatus(struct dispc_device *dispc, in dispc_k2g_vid_write_irqstatus() argument
575 dispc_vid_write(dispc, hw_plane, DISPC_VID_K2G_IRQSTATUS, stat); in dispc_k2g_vid_write_irqstatus()
578 static dispc_irq_t dispc_k2g_vp_read_irqenable(struct dispc_device *dispc, in dispc_k2g_vp_read_irqenable() argument
581 u32 stat = dispc_vp_read(dispc, hw_videoport, DISPC_VP_K2G_IRQENABLE); in dispc_k2g_vp_read_irqenable()
586 static void dispc_k2g_vp_set_irqenable(struct dispc_device *dispc, in dispc_k2g_vp_set_irqenable() argument
591 dispc_vp_write(dispc, hw_videoport, DISPC_VP_K2G_IRQENABLE, stat); in dispc_k2g_vp_set_irqenable()
594 static dispc_irq_t dispc_k2g_vid_read_irqenable(struct dispc_device *dispc, in dispc_k2g_vid_read_irqenable() argument
597 u32 stat = dispc_vid_read(dispc, hw_plane, DISPC_VID_K2G_IRQENABLE); in dispc_k2g_vid_read_irqenable()
602 static void dispc_k2g_vid_set_irqenable(struct dispc_device *dispc, in dispc_k2g_vid_set_irqenable() argument
607 dispc_vid_write(dispc, hw_plane, DISPC_VID_K2G_IRQENABLE, stat); in dispc_k2g_vid_set_irqenable()
610 static void dispc_k2g_clear_irqstatus(struct dispc_device *dispc, in dispc_k2g_clear_irqstatus() argument
613 dispc_k2g_vp_write_irqstatus(dispc, 0, mask); in dispc_k2g_clear_irqstatus()
614 dispc_k2g_vid_write_irqstatus(dispc, 0, mask); in dispc_k2g_clear_irqstatus()
618 dispc_irq_t dispc_k2g_read_and_clear_irqstatus(struct dispc_device *dispc) in dispc_k2g_read_and_clear_irqstatus() argument
623 dispc_write(dispc, DISPC_IRQSTATUS, in dispc_k2g_read_and_clear_irqstatus()
624 dispc_read(dispc, DISPC_IRQSTATUS)); in dispc_k2g_read_and_clear_irqstatus()
626 stat |= dispc_k2g_vp_read_irqstatus(dispc, 0); in dispc_k2g_read_and_clear_irqstatus()
627 stat |= dispc_k2g_vid_read_irqstatus(dispc, 0); in dispc_k2g_read_and_clear_irqstatus()
629 dispc_k2g_clear_irqstatus(dispc, stat); in dispc_k2g_read_and_clear_irqstatus()
634 static dispc_irq_t dispc_k2g_read_irqenable(struct dispc_device *dispc) in dispc_k2g_read_irqenable() argument
638 stat |= dispc_k2g_vp_read_irqenable(dispc, 0); in dispc_k2g_read_irqenable()
639 stat |= dispc_k2g_vid_read_irqenable(dispc, 0); in dispc_k2g_read_irqenable()
645 void dispc_k2g_set_irqenable(struct dispc_device *dispc, dispc_irq_t mask) in dispc_k2g_set_irqenable() argument
647 dispc_irq_t old_mask = dispc_k2g_read_irqenable(dispc); in dispc_k2g_set_irqenable()
650 dispc_k2g_clear_irqstatus(dispc, (mask ^ old_mask) & mask); in dispc_k2g_set_irqenable()
652 dispc_k2g_vp_set_irqenable(dispc, 0, mask); in dispc_k2g_set_irqenable()
653 dispc_k2g_vid_set_irqenable(dispc, 0, mask); in dispc_k2g_set_irqenable()
655 dispc_write(dispc, DISPC_IRQENABLE_SET, (1 << 0) | (1 << 7)); in dispc_k2g_set_irqenable()
658 dispc_k2g_read_irqenable(dispc); in dispc_k2g_set_irqenable()
661 static dispc_irq_t dispc_k3_vp_read_irqstatus(struct dispc_device *dispc, in dispc_k3_vp_read_irqstatus() argument
664 u32 stat = dispc_read(dispc, DISPC_VP_IRQSTATUS(hw_videoport)); in dispc_k3_vp_read_irqstatus()
669 static void dispc_k3_vp_write_irqstatus(struct dispc_device *dispc, in dispc_k3_vp_write_irqstatus() argument
674 dispc_write(dispc, DISPC_VP_IRQSTATUS(hw_videoport), stat); in dispc_k3_vp_write_irqstatus()
677 static dispc_irq_t dispc_k3_vid_read_irqstatus(struct dispc_device *dispc, in dispc_k3_vid_read_irqstatus() argument
680 u32 stat = dispc_read(dispc, DISPC_VID_IRQSTATUS(hw_plane)); in dispc_k3_vid_read_irqstatus()
685 static void dispc_k3_vid_write_irqstatus(struct dispc_device *dispc, in dispc_k3_vid_write_irqstatus() argument
690 dispc_write(dispc, DISPC_VID_IRQSTATUS(hw_plane), stat); in dispc_k3_vid_write_irqstatus()
693 static dispc_irq_t dispc_k3_vp_read_irqenable(struct dispc_device *dispc, in dispc_k3_vp_read_irqenable() argument
696 u32 stat = dispc_read(dispc, DISPC_VP_IRQENABLE(hw_videoport)); in dispc_k3_vp_read_irqenable()
701 static void dispc_k3_vp_set_irqenable(struct dispc_device *dispc, in dispc_k3_vp_set_irqenable() argument
706 dispc_write(dispc, DISPC_VP_IRQENABLE(hw_videoport), stat); in dispc_k3_vp_set_irqenable()
709 static dispc_irq_t dispc_k3_vid_read_irqenable(struct dispc_device *dispc, in dispc_k3_vid_read_irqenable() argument
712 u32 stat = dispc_read(dispc, DISPC_VID_IRQENABLE(hw_plane)); in dispc_k3_vid_read_irqenable()
717 static void dispc_k3_vid_set_irqenable(struct dispc_device *dispc, in dispc_k3_vid_set_irqenable() argument
722 dispc_write(dispc, DISPC_VID_IRQENABLE(hw_plane), stat); in dispc_k3_vid_set_irqenable()
726 void dispc_k3_clear_irqstatus(struct dispc_device *dispc, dispc_irq_t clearmask) in dispc_k3_clear_irqstatus() argument
731 for (i = 0; i < dispc->feat->num_vps; ++i) { in dispc_k3_clear_irqstatus()
733 dispc_k3_vp_write_irqstatus(dispc, i, clearmask); in dispc_k3_clear_irqstatus()
737 for (i = 0; i < dispc->feat->num_planes; ++i) { in dispc_k3_clear_irqstatus()
739 dispc_k3_vid_write_irqstatus(dispc, i, clearmask); in dispc_k3_clear_irqstatus()
743 if (dispc->feat->subrev == DISPC_K2G) in dispc_k3_clear_irqstatus()
746 dispc_write(dispc, DISPC_IRQSTATUS, top_clear); in dispc_k3_clear_irqstatus()
749 dispc_read(dispc, DISPC_IRQSTATUS); in dispc_k3_clear_irqstatus()
753 dispc_irq_t dispc_k3_read_and_clear_irqstatus(struct dispc_device *dispc) in dispc_k3_read_and_clear_irqstatus() argument
758 for (i = 0; i < dispc->feat->num_vps; ++i) in dispc_k3_read_and_clear_irqstatus()
759 status |= dispc_k3_vp_read_irqstatus(dispc, i); in dispc_k3_read_and_clear_irqstatus()
761 for (i = 0; i < dispc->feat->num_planes; ++i) in dispc_k3_read_and_clear_irqstatus()
762 status |= dispc_k3_vid_read_irqstatus(dispc, i); in dispc_k3_read_and_clear_irqstatus()
764 dispc_k3_clear_irqstatus(dispc, status); in dispc_k3_read_and_clear_irqstatus()
769 static dispc_irq_t dispc_k3_read_irqenable(struct dispc_device *dispc) in dispc_k3_read_irqenable() argument
774 for (i = 0; i < dispc->feat->num_vps; ++i) in dispc_k3_read_irqenable()
775 enable |= dispc_k3_vp_read_irqenable(dispc, i); in dispc_k3_read_irqenable()
777 for (i = 0; i < dispc->feat->num_planes; ++i) in dispc_k3_read_irqenable()
778 enable |= dispc_k3_vid_read_irqenable(dispc, i); in dispc_k3_read_irqenable()
783 static void dispc_k3_set_irqenable(struct dispc_device *dispc, in dispc_k3_set_irqenable() argument
790 old_mask = dispc_k3_read_irqenable(dispc); in dispc_k3_set_irqenable()
793 dispc_k3_clear_irqstatus(dispc, (old_mask ^ mask) & mask); in dispc_k3_set_irqenable()
795 for (i = 0; i < dispc->feat->num_vps; ++i) { in dispc_k3_set_irqenable()
796 dispc_k3_vp_set_irqenable(dispc, i, mask); in dispc_k3_set_irqenable()
803 for (i = 0; i < dispc->feat->num_planes; ++i) { in dispc_k3_set_irqenable()
804 dispc_k3_vid_set_irqenable(dispc, i, mask); in dispc_k3_set_irqenable()
812 dispc_write(dispc, DISPC_IRQENABLE_SET, main_enable); in dispc_k3_set_irqenable()
815 dispc_write(dispc, DISPC_IRQENABLE_CLR, main_disable); in dispc_k3_set_irqenable()
818 dispc_read(dispc, DISPC_IRQENABLE_SET); in dispc_k3_set_irqenable()
821 dispc_irq_t dispc_read_and_clear_irqstatus(struct dispc_device *dispc) in dispc_read_and_clear_irqstatus() argument
823 switch (dispc->feat->subrev) { in dispc_read_and_clear_irqstatus()
825 return dispc_k2g_read_and_clear_irqstatus(dispc); in dispc_read_and_clear_irqstatus()
829 return dispc_k3_read_and_clear_irqstatus(dispc); in dispc_read_and_clear_irqstatus()
836 void dispc_set_irqenable(struct dispc_device *dispc, dispc_irq_t mask) in dispc_set_irqenable() argument
838 switch (dispc->feat->subrev) { in dispc_set_irqenable()
840 dispc_k2g_set_irqenable(dispc, mask); in dispc_set_irqenable()
845 dispc_k3_set_irqenable(dispc, mask); in dispc_set_irqenable()
875 struct dispc_bus_format *dispc_vp_find_bus_fmt(struct dispc_device *dispc, in dispc_vp_find_bus_fmt() argument
889 int dispc_vp_bus_check(struct dispc_device *dispc, u32 hw_videoport, in dispc_vp_bus_check() argument
895 fmt = dispc_vp_find_bus_fmt(dispc, hw_videoport, tstate->bus_format, in dispc_vp_bus_check()
898 dev_dbg(dispc->dev, "%s: Unsupported bus format: %u\n", in dispc_vp_bus_check()
903 if (dispc->feat->vp_bus_type[hw_videoport] != DISPC_VP_OLDI && in dispc_vp_bus_check()
905 dev_dbg(dispc->dev, "%s: %s is not OLDI-port\n", in dispc_vp_bus_check()
906 __func__, dispc->feat->vp_name[hw_videoport]); in dispc_vp_bus_check()
913 static void dispc_oldi_tx_power(struct dispc_device *dispc, bool power) in dispc_oldi_tx_power() argument
917 if (WARN_ON(!dispc->oldi_io_ctrl)) in dispc_oldi_tx_power()
920 regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT0_IO_CTRL, in dispc_oldi_tx_power()
922 regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT1_IO_CTRL, in dispc_oldi_tx_power()
924 regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT2_IO_CTRL, in dispc_oldi_tx_power()
926 regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT3_IO_CTRL, in dispc_oldi_tx_power()
928 regmap_update_bits(dispc->oldi_io_ctrl, OLDI_CLK_IO_CTRL, in dispc_oldi_tx_power()
932 static void dispc_set_num_datalines(struct dispc_device *dispc, in dispc_set_num_datalines() argument
955 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, v, 10, 8); in dispc_set_num_datalines()
958 static void dispc_enable_oldi(struct dispc_device *dispc, u32 hw_videoport, in dispc_enable_oldi() argument
973 dev_warn(dispc->dev, "%s: %d port width not supported\n", in dispc_enable_oldi()
984 dispc_vp_write(dispc, hw_videoport, DISPC_VP_DSS_OLDI_CFG, oldi_cfg); in dispc_enable_oldi()
986 while (!(oldi_reset_bit & dispc_read(dispc, DSS_SYSSTATUS)) && in dispc_enable_oldi()
990 if (!(oldi_reset_bit & dispc_read(dispc, DSS_SYSSTATUS))) in dispc_enable_oldi()
991 dev_warn(dispc->dev, "%s: timeout waiting OLDI reset done\n", in dispc_enable_oldi()
995 void dispc_vp_prepare(struct dispc_device *dispc, u32 hw_videoport, in dispc_vp_prepare() argument
1001 fmt = dispc_vp_find_bus_fmt(dispc, hw_videoport, tstate->bus_format, in dispc_vp_prepare()
1007 if (dispc->feat->vp_bus_type[hw_videoport] == DISPC_VP_OLDI) { in dispc_vp_prepare()
1008 dispc_oldi_tx_power(dispc, true); in dispc_vp_prepare()
1010 dispc_enable_oldi(dispc, hw_videoport, fmt); in dispc_vp_prepare()
1014 void dispc_vp_enable(struct dispc_device *dispc, u32 hw_videoport, in dispc_vp_enable() argument
1023 fmt = dispc_vp_find_bus_fmt(dispc, hw_videoport, tstate->bus_format, in dispc_vp_enable()
1029 dispc_set_num_datalines(dispc, hw_videoport, fmt->data_width); in dispc_vp_enable()
1039 dispc_vp_write(dispc, hw_videoport, DISPC_VP_TIMING_H, in dispc_vp_enable()
1044 dispc_vp_write(dispc, hw_videoport, DISPC_VP_TIMING_V, in dispc_vp_enable()
1066 if (dispc->feat->vp_bus_type[hw_videoport] == DISPC_VP_OLDI) in dispc_vp_enable()
1069 dispc_vp_write(dispc, hw_videoport, DISPC_VP_POL_FREQ, in dispc_vp_enable()
1078 dispc_vp_write(dispc, hw_videoport, DISPC_VP_SIZE_SCREEN, in dispc_vp_enable()
1082 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1, 0, 0); in dispc_vp_enable()
1085 void dispc_vp_disable(struct dispc_device *dispc, u32 hw_videoport) in dispc_vp_disable() argument
1087 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 0, 0, 0); in dispc_vp_disable()
1090 void dispc_vp_unprepare(struct dispc_device *dispc, u32 hw_videoport) in dispc_vp_unprepare() argument
1092 if (dispc->feat->vp_bus_type[hw_videoport] == DISPC_VP_OLDI) { in dispc_vp_unprepare()
1093 dispc_vp_write(dispc, hw_videoport, DISPC_VP_DSS_OLDI_CFG, 0); in dispc_vp_unprepare()
1095 dispc_oldi_tx_power(dispc, false); in dispc_vp_unprepare()
1099 bool dispc_vp_go_busy(struct dispc_device *dispc, u32 hw_videoport) in dispc_vp_go_busy() argument
1101 return VP_REG_GET(dispc, hw_videoport, DISPC_VP_CONTROL, 5, 5); in dispc_vp_go_busy()
1104 void dispc_vp_go(struct dispc_device *dispc, u32 hw_videoport) in dispc_vp_go() argument
1106 WARN_ON(VP_REG_GET(dispc, hw_videoport, DISPC_VP_CONTROL, 5, 5)); in dispc_vp_go()
1107 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1, 5, 5); in dispc_vp_go()
1150 static void dispc_vp_set_default_color(struct dispc_device *dispc, in dispc_vp_set_default_color() argument
1157 dispc_ovr_write(dispc, hw_videoport, in dispc_vp_set_default_color()
1159 dispc_ovr_write(dispc, hw_videoport, in dispc_vp_set_default_color()
1163 enum drm_mode_status dispc_vp_mode_valid(struct dispc_device *dispc, in dispc_vp_mode_valid() argument
1171 bus_type = dispc->feat->vp_bus_type[hw_videoport]; in dispc_vp_mode_valid()
1173 max_pclk = dispc->feat->max_pclk_khz[bus_type]; in dispc_vp_mode_valid()
1178 if (mode->clock < dispc->feat->min_pclk_khz) in dispc_vp_mode_valid()
1222 if (dispc->memory_bandwidth_limit) { in dispc_vp_mode_valid()
1230 if (dispc->memory_bandwidth_limit < bandwidth) in dispc_vp_mode_valid()
1237 int dispc_vp_enable_clk(struct dispc_device *dispc, u32 hw_videoport) in dispc_vp_enable_clk() argument
1239 int ret = clk_prepare_enable(dispc->vp_clk[hw_videoport]); in dispc_vp_enable_clk()
1242 dev_err(dispc->dev, "%s: enabling clk failed: %d\n", __func__, in dispc_vp_enable_clk()
1248 void dispc_vp_disable_clk(struct dispc_device *dispc, u32 hw_videoport) in dispc_vp_disable_clk() argument
1250 clk_disable_unprepare(dispc->vp_clk[hw_videoport]); in dispc_vp_disable_clk()
1265 int dispc_vp_set_clk_rate(struct dispc_device *dispc, u32 hw_videoport, in dispc_vp_set_clk_rate() argument
1271 r = clk_set_rate(dispc->vp_clk[hw_videoport], rate); in dispc_vp_set_clk_rate()
1273 dev_err(dispc->dev, "vp%d: failed to set clk rate to %lu\n", in dispc_vp_set_clk_rate()
1278 new_rate = clk_get_rate(dispc->vp_clk[hw_videoport]); in dispc_vp_set_clk_rate()
1281 dev_warn(dispc->dev, in dispc_vp_set_clk_rate()
1285 dev_dbg(dispc->dev, "vp%d: new rate %lu Hz (requested %lu Hz)\n", in dispc_vp_set_clk_rate()
1286 hw_videoport, clk_get_rate(dispc->vp_clk[hw_videoport]), rate); in dispc_vp_set_clk_rate()
1292 static void dispc_k2g_ovr_set_plane(struct dispc_device *dispc, in dispc_k2g_ovr_set_plane() argument
1297 dispc_vid_write(dispc, hw_plane, DISPC_VID_K2G_POSITION, in dispc_k2g_ovr_set_plane()
1301 static void dispc_am65x_ovr_set_plane(struct dispc_device *dispc, in dispc_am65x_ovr_set_plane() argument
1305 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), in dispc_am65x_ovr_set_plane()
1307 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), in dispc_am65x_ovr_set_plane()
1309 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), in dispc_am65x_ovr_set_plane()
1313 static void dispc_j721e_ovr_set_plane(struct dispc_device *dispc, in dispc_j721e_ovr_set_plane() argument
1317 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), in dispc_j721e_ovr_set_plane()
1319 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES2(layer), in dispc_j721e_ovr_set_plane()
1321 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES2(layer), in dispc_j721e_ovr_set_plane()
1325 void dispc_ovr_set_plane(struct dispc_device *dispc, u32 hw_plane, in dispc_ovr_set_plane() argument
1328 switch (dispc->feat->subrev) { in dispc_ovr_set_plane()
1330 dispc_k2g_ovr_set_plane(dispc, hw_plane, hw_videoport, in dispc_ovr_set_plane()
1335 dispc_am65x_ovr_set_plane(dispc, hw_plane, hw_videoport, in dispc_ovr_set_plane()
1339 dispc_j721e_ovr_set_plane(dispc, hw_plane, hw_videoport, in dispc_ovr_set_plane()
1348 void dispc_ovr_enable_layer(struct dispc_device *dispc, in dispc_ovr_enable_layer() argument
1351 if (dispc->feat->subrev == DISPC_K2G) in dispc_ovr_enable_layer()
1354 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), in dispc_ovr_enable_layer()
1437 static void dispc_k2g_vid_write_csc(struct dispc_device *dispc, u32 hw_plane, in dispc_k2g_vid_write_csc() argument
1452 dev_warn(dispc->dev, "%s: No post offset support for %s\n", in dispc_k2g_vid_write_csc()
1456 dispc_vid_write(dispc, hw_plane, dispc_vid_csc_coef_reg[i], in dispc_k2g_vid_write_csc()
1460 static void dispc_k3_vid_write_csc(struct dispc_device *dispc, u32 hw_plane, in dispc_k3_vid_write_csc() argument
1475 dispc_vid_write(dispc, hw_plane, dispc_vid_csc_coef_reg[i], in dispc_k3_vid_write_csc()
1557 static void dispc_vid_csc_setup(struct dispc_device *dispc, u32 hw_plane, in dispc_vid_csc_setup() argument
1564 dev_err(dispc->dev, "%s: CSC (%u,%u) not found\n", in dispc_vid_csc_setup()
1569 if (dispc->feat->subrev == DISPC_K2G) in dispc_vid_csc_setup()
1570 dispc_k2g_vid_write_csc(dispc, hw_plane, coef); in dispc_vid_csc_setup()
1572 dispc_k3_vid_write_csc(dispc, hw_plane, coef); in dispc_vid_csc_setup()
1575 static void dispc_vid_csc_enable(struct dispc_device *dispc, u32 hw_plane, in dispc_vid_csc_enable() argument
1578 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, !!enable, 9, 9); in dispc_vid_csc_enable()
1595 static void dispc_vid_write_fir_coefs(struct dispc_device *dispc, in dispc_vid_write_fir_coefs() argument
1619 dev_err(dispc->dev, "%s: No coefficients given.\n", __func__); in dispc_vid_write_fir_coefs()
1627 dispc_vid_write(dispc, hw_plane, reg, c0); in dispc_vid_write_fir_coefs()
1639 dispc_vid_write(dispc, hw_plane, reg, c12); in dispc_vid_write_fir_coefs()
1664 static int dispc_vid_calc_scaling(struct dispc_device *dispc, in dispc_vid_calc_scaling() argument
1669 const struct dispc_features_scaling *f = &dispc->feat->scaling; in dispc_vid_calc_scaling()
1718 dev_dbg(dispc->dev, in dispc_vid_calc_scaling()
1731 dev_dbg(dispc->dev, in dispc_vid_calc_scaling()
1748 dev_dbg(dispc->dev, in dispc_vid_calc_scaling()
1769 dev_dbg(dispc->dev, in dispc_vid_calc_scaling()
1787 dev_dbg(dispc->dev, in dispc_vid_calc_scaling()
1803 sp->xcoef_uv = tidss_get_scale_coefs(dispc->dev, in dispc_vid_calc_scaling()
1811 sp->ycoef_uv = tidss_get_scale_coefs(dispc->dev, in dispc_vid_calc_scaling()
1818 sp->xcoef = tidss_get_scale_coefs(dispc->dev, sp->fir_xinc, in dispc_vid_calc_scaling()
1822 sp->ycoef = tidss_get_scale_coefs(dispc->dev, sp->fir_yinc, in dispc_vid_calc_scaling()
1828 static void dispc_vid_set_scaling(struct dispc_device *dispc, in dispc_vid_set_scaling() argument
1834 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, in dispc_vid_set_scaling()
1838 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, in dispc_vid_set_scaling()
1846 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, in dispc_vid_set_scaling()
1851 dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRH2, in dispc_vid_set_scaling()
1853 dispc_vid_write_fir_coefs(dispc, hw_plane, in dispc_vid_set_scaling()
1858 dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRV2, in dispc_vid_set_scaling()
1860 dispc_vid_write_fir_coefs(dispc, hw_plane, in dispc_vid_set_scaling()
1867 dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRH, sp->fir_xinc); in dispc_vid_set_scaling()
1868 dispc_vid_write_fir_coefs(dispc, hw_plane, in dispc_vid_set_scaling()
1874 dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRV, sp->fir_yinc); in dispc_vid_set_scaling()
1875 dispc_vid_write_fir_coefs(dispc, hw_plane, in dispc_vid_set_scaling()
1928 static void dispc_plane_set_pixel_format(struct dispc_device *dispc, in dispc_plane_set_pixel_format() argument
1935 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, in dispc_plane_set_pixel_format()
1945 const u32 *dispc_plane_formats(struct dispc_device *dispc, unsigned int *len) in dispc_plane_formats() argument
1947 WARN_ON(!dispc->fourccs); in dispc_plane_formats()
1949 *len = dispc->num_fourccs; in dispc_plane_formats()
1951 return dispc->fourccs; in dispc_plane_formats()
1967 int dispc_plane_check(struct dispc_device *dispc, u32 hw_plane, in dispc_plane_check() argument
1971 bool lite = dispc->feat->vid_lite[hw_plane]; in dispc_plane_check()
1981 dev_dbg(dispc->dev, in dispc_plane_check()
1991 dev_dbg(dispc->dev, in dispc_plane_check()
1998 ret = dispc_vid_calc_scaling(dispc, state, &scaling, false); in dispc_plane_check()
2038 void dispc_plane_setup(struct dispc_device *dispc, u32 hw_plane, in dispc_plane_setup() argument
2042 bool lite = dispc->feat->vid_lite[hw_plane]; in dispc_plane_setup()
2049 dispc_vid_calc_scaling(dispc, state, &scale, lite); in dispc_plane_setup()
2051 dispc_plane_set_pixel_format(dispc, hw_plane, fourcc); in dispc_plane_setup()
2053 dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_0, dma_addr & 0xffffffff); in dispc_plane_setup()
2054 dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_EXT_0, (u64)dma_addr >> 32); in dispc_plane_setup()
2055 dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_1, dma_addr & 0xffffffff); in dispc_plane_setup()
2056 dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_EXT_1, (u64)dma_addr >> 32); in dispc_plane_setup()
2058 dispc_vid_write(dispc, hw_plane, DISPC_VID_PICTURE_SIZE, in dispc_plane_setup()
2063 dispc_vid_write(dispc, hw_plane, DISPC_VID_PIXEL_INC, in dispc_plane_setup()
2066 dispc_vid_write(dispc, hw_plane, DISPC_VID_PIXEL_INC, in dispc_plane_setup()
2069 dispc_vid_write(dispc, hw_plane, DISPC_VID_ROW_INC, in dispc_plane_setup()
2079 dispc_vid_write(dispc, hw_plane, in dispc_plane_setup()
2081 dispc_vid_write(dispc, hw_plane, in dispc_plane_setup()
2083 dispc_vid_write(dispc, hw_plane, in dispc_plane_setup()
2085 dispc_vid_write(dispc, hw_plane, in dispc_plane_setup()
2088 dispc_vid_write(dispc, hw_plane, DISPC_VID_ROW_INC_UV, in dispc_plane_setup()
2095 dispc_vid_write(dispc, hw_plane, DISPC_VID_SIZE, in dispc_plane_setup()
2099 dispc_vid_set_scaling(dispc, hw_plane, &scale, fourcc); in dispc_plane_setup()
2104 dispc_vid_csc_setup(dispc, hw_plane, state); in dispc_plane_setup()
2105 dispc_vid_csc_enable(dispc, hw_plane, true); in dispc_plane_setup()
2107 dispc_vid_csc_enable(dispc, hw_plane, false); in dispc_plane_setup()
2110 dispc_vid_write(dispc, hw_plane, DISPC_VID_GLOBAL_ALPHA, in dispc_plane_setup()
2114 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 1, in dispc_plane_setup()
2117 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 0, in dispc_plane_setup()
2121 void dispc_plane_enable(struct dispc_device *dispc, u32 hw_plane, bool enable) in dispc_plane_enable() argument
2123 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, !!enable, 0, 0); in dispc_plane_enable()
2126 static u32 dispc_vid_get_fifo_size(struct dispc_device *dispc, u32 hw_plane) in dispc_vid_get_fifo_size() argument
2128 return VID_REG_GET(dispc, hw_plane, DISPC_VID_BUF_SIZE_STATUS, 15, 0); in dispc_vid_get_fifo_size()
2131 static void dispc_vid_set_mflag_threshold(struct dispc_device *dispc, in dispc_vid_set_mflag_threshold() argument
2134 dispc_vid_write(dispc, hw_plane, DISPC_VID_MFLAG_THRESHOLD, in dispc_vid_set_mflag_threshold()
2138 static void dispc_vid_set_buf_threshold(struct dispc_device *dispc, in dispc_vid_set_buf_threshold() argument
2141 dispc_vid_write(dispc, hw_plane, DISPC_VID_BUF_THRESHOLD, in dispc_vid_set_buf_threshold()
2145 static void dispc_k2g_plane_init(struct dispc_device *dispc) in dispc_k2g_plane_init() argument
2149 dev_dbg(dispc->dev, "%s()\n", __func__); in dispc_k2g_plane_init()
2152 REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 2, 1, 0); in dispc_k2g_plane_init()
2154 REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 0, 6, 6); in dispc_k2g_plane_init()
2156 for (hw_plane = 0; hw_plane < dispc->feat->num_planes; hw_plane++) { in dispc_k2g_plane_init()
2157 u32 size = dispc_vid_get_fifo_size(dispc, hw_plane); in dispc_k2g_plane_init()
2170 dev_dbg(dispc->dev, in dispc_k2g_plane_init()
2172 dispc->feat->vid_name[hw_plane], in dispc_k2g_plane_init()
2178 dispc_vid_set_buf_threshold(dispc, hw_plane, in dispc_k2g_plane_init()
2180 dispc_vid_set_mflag_threshold(dispc, hw_plane, in dispc_k2g_plane_init()
2183 dispc_vid_write(dispc, hw_plane, DISPC_VID_PRELOAD, preload); in dispc_k2g_plane_init()
2190 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 1, in dispc_k2g_plane_init()
2195 static void dispc_k3_plane_init(struct dispc_device *dispc) in dispc_k3_plane_init() argument
2201 dev_dbg(dispc->dev, "%s()\n", __func__); in dispc_k3_plane_init()
2203 REG_FLD_MOD(dispc, DSS_CBA_CFG, cba_lo_pri, 2, 0); in dispc_k3_plane_init()
2204 REG_FLD_MOD(dispc, DSS_CBA_CFG, cba_hi_pri, 5, 3); in dispc_k3_plane_init()
2207 REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 2, 1, 0); in dispc_k3_plane_init()
2209 REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 0, 6, 6); in dispc_k3_plane_init()
2211 for (hw_plane = 0; hw_plane < dispc->feat->num_planes; hw_plane++) { in dispc_k3_plane_init()
2212 u32 size = dispc_vid_get_fifo_size(dispc, hw_plane); in dispc_k3_plane_init()
2225 dev_dbg(dispc->dev, in dispc_k3_plane_init()
2227 dispc->feat->vid_name[hw_plane], in dispc_k3_plane_init()
2233 dispc_vid_set_buf_threshold(dispc, hw_plane, in dispc_k3_plane_init()
2235 dispc_vid_set_mflag_threshold(dispc, hw_plane, in dispc_k3_plane_init()
2238 dispc_vid_write(dispc, hw_plane, DISPC_VID_PRELOAD, preload); in dispc_k3_plane_init()
2241 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 0, in dispc_k3_plane_init()
2246 static void dispc_plane_init(struct dispc_device *dispc) in dispc_plane_init() argument
2248 switch (dispc->feat->subrev) { in dispc_plane_init()
2250 dispc_k2g_plane_init(dispc); in dispc_plane_init()
2255 dispc_k3_plane_init(dispc); in dispc_plane_init()
2262 static void dispc_vp_init(struct dispc_device *dispc) in dispc_vp_init() argument
2266 dev_dbg(dispc->dev, "%s()\n", __func__); in dispc_vp_init()
2269 for (i = 0; i < dispc->feat->num_vps; i++) in dispc_vp_init()
2270 VP_REG_FLD_MOD(dispc, i, DISPC_VP_CONFIG, 1, 2, 2); in dispc_vp_init()
2273 static void dispc_initial_config(struct dispc_device *dispc) in dispc_initial_config() argument
2275 dispc_plane_init(dispc); in dispc_initial_config()
2276 dispc_vp_init(dispc); in dispc_initial_config()
2279 if (dispc->feat->subrev == DISPC_J721E) { in dispc_initial_config()
2280 dispc_write(dispc, DISPC_CONNECTIONS, in dispc_initial_config()
2287 static void dispc_k2g_vp_write_gamma_table(struct dispc_device *dispc, in dispc_k2g_vp_write_gamma_table() argument
2290 u32 *table = dispc->vp_data[hw_videoport].gamma_table; in dispc_k2g_vp_write_gamma_table()
2291 u32 hwlen = dispc->feat->vp_feat.color.gamma_size; in dispc_k2g_vp_write_gamma_table()
2294 dev_dbg(dispc->dev, "%s: hw_videoport %d\n", __func__, hw_videoport); in dispc_k2g_vp_write_gamma_table()
2296 if (WARN_ON(dispc->feat->vp_feat.color.gamma_type != TIDSS_GAMMA_8BIT)) in dispc_k2g_vp_write_gamma_table()
2304 dispc_vp_write(dispc, hw_videoport, DISPC_VP_K2G_GAMMA_TABLE, in dispc_k2g_vp_write_gamma_table()
2309 static void dispc_am65x_vp_write_gamma_table(struct dispc_device *dispc, in dispc_am65x_vp_write_gamma_table() argument
2312 u32 *table = dispc->vp_data[hw_videoport].gamma_table; in dispc_am65x_vp_write_gamma_table()
2313 u32 hwlen = dispc->feat->vp_feat.color.gamma_size; in dispc_am65x_vp_write_gamma_table()
2316 dev_dbg(dispc->dev, "%s: hw_videoport %d\n", __func__, hw_videoport); in dispc_am65x_vp_write_gamma_table()
2318 if (WARN_ON(dispc->feat->vp_feat.color.gamma_type != TIDSS_GAMMA_8BIT)) in dispc_am65x_vp_write_gamma_table()
2326 dispc_vp_write(dispc, hw_videoport, DISPC_VP_GAMMA_TABLE, v); in dispc_am65x_vp_write_gamma_table()
2330 static void dispc_j721e_vp_write_gamma_table(struct dispc_device *dispc, in dispc_j721e_vp_write_gamma_table() argument
2333 u32 *table = dispc->vp_data[hw_videoport].gamma_table; in dispc_j721e_vp_write_gamma_table()
2334 u32 hwlen = dispc->feat->vp_feat.color.gamma_size; in dispc_j721e_vp_write_gamma_table()
2337 dev_dbg(dispc->dev, "%s: hw_videoport %d\n", __func__, hw_videoport); in dispc_j721e_vp_write_gamma_table()
2339 if (WARN_ON(dispc->feat->vp_feat.color.gamma_type != TIDSS_GAMMA_10BIT)) in dispc_j721e_vp_write_gamma_table()
2348 dispc_vp_write(dispc, hw_videoport, DISPC_VP_GAMMA_TABLE, v); in dispc_j721e_vp_write_gamma_table()
2352 static void dispc_vp_write_gamma_table(struct dispc_device *dispc, in dispc_vp_write_gamma_table() argument
2355 switch (dispc->feat->subrev) { in dispc_vp_write_gamma_table()
2357 dispc_k2g_vp_write_gamma_table(dispc, hw_videoport); in dispc_vp_write_gamma_table()
2361 dispc_am65x_vp_write_gamma_table(dispc, hw_videoport); in dispc_vp_write_gamma_table()
2364 dispc_j721e_vp_write_gamma_table(dispc, hw_videoport); in dispc_vp_write_gamma_table()
2377 static void dispc_vp_set_gamma(struct dispc_device *dispc, in dispc_vp_set_gamma() argument
2382 u32 *table = dispc->vp_data[hw_videoport].gamma_table; in dispc_vp_set_gamma()
2383 u32 hwlen = dispc->feat->vp_feat.color.gamma_size; in dispc_vp_set_gamma()
2387 dev_dbg(dispc->dev, "%s: hw_videoport %d, lut len %u, hw len %u\n", in dispc_vp_set_gamma()
2390 if (dispc->feat->vp_feat.color.gamma_type == TIDSS_GAMMA_10BIT) in dispc_vp_set_gamma()
2424 dispc_vp_write_gamma_table(dispc, hw_videoport); in dispc_vp_set_gamma()
2471 static void dispc_k2g_vp_write_csc(struct dispc_device *dispc, u32 hw_videoport, in dispc_k2g_vp_write_csc() argument
2484 dispc_vp_write(dispc, hw_videoport, dispc_vp_cpr_coef_reg[i], in dispc_k2g_vp_write_csc()
2488 static void dispc_k2g_vp_set_ctm(struct dispc_device *dispc, u32 hw_videoport, in dispc_k2g_vp_set_ctm() argument
2497 dispc_k2g_vp_write_csc(dispc, hw_videoport, &cpr); in dispc_k2g_vp_set_ctm()
2501 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONFIG, in dispc_k2g_vp_set_ctm()
2536 static void dispc_k3_vp_write_csc(struct dispc_device *dispc, u32 hw_videoport, in dispc_k3_vp_write_csc() argument
2550 dispc_vp_write(dispc, hw_videoport, dispc_vp_csc_coef_reg[i], in dispc_k3_vp_write_csc()
2554 static void dispc_k3_vp_set_ctm(struct dispc_device *dispc, u32 hw_videoport, in dispc_k3_vp_set_ctm() argument
2563 dispc_k3_vp_write_csc(dispc, hw_videoport, &csc); in dispc_k3_vp_set_ctm()
2567 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONFIG, in dispc_k3_vp_set_ctm()
2571 static void dispc_vp_set_color_mgmt(struct dispc_device *dispc, in dispc_vp_set_color_mgmt() argument
2588 dispc_vp_set_gamma(dispc, hw_videoport, lut, length); in dispc_vp_set_color_mgmt()
2593 if (dispc->feat->subrev == DISPC_K2G) in dispc_vp_set_color_mgmt()
2594 dispc_k2g_vp_set_ctm(dispc, hw_videoport, ctm); in dispc_vp_set_color_mgmt()
2596 dispc_k3_vp_set_ctm(dispc, hw_videoport, ctm); in dispc_vp_set_color_mgmt()
2599 void dispc_vp_setup(struct dispc_device *dispc, u32 hw_videoport, in dispc_vp_setup() argument
2602 dispc_vp_set_default_color(dispc, hw_videoport, 0); in dispc_vp_setup()
2603 dispc_vp_set_color_mgmt(dispc, hw_videoport, state, newmodeset); in dispc_vp_setup()
2606 int dispc_runtime_suspend(struct dispc_device *dispc) in dispc_runtime_suspend() argument
2608 dev_dbg(dispc->dev, "suspend\n"); in dispc_runtime_suspend()
2610 dispc->is_enabled = false; in dispc_runtime_suspend()
2612 clk_disable_unprepare(dispc->fclk); in dispc_runtime_suspend()
2617 int dispc_runtime_resume(struct dispc_device *dispc) in dispc_runtime_resume() argument
2619 dev_dbg(dispc->dev, "resume\n"); in dispc_runtime_resume()
2621 clk_prepare_enable(dispc->fclk); in dispc_runtime_resume()
2623 if (REG_GET(dispc, DSS_SYSSTATUS, 0, 0) == 0) in dispc_runtime_resume()
2624 dev_warn(dispc->dev, "DSS FUNC RESET not done!\n"); in dispc_runtime_resume()
2626 dev_dbg(dispc->dev, "OMAP DSS7 rev 0x%x\n", in dispc_runtime_resume()
2627 dispc_read(dispc, DSS_REVISION)); in dispc_runtime_resume()
2629 dev_dbg(dispc->dev, "VP RESETDONE %d,%d,%d\n", in dispc_runtime_resume()
2630 REG_GET(dispc, DSS_SYSSTATUS, 1, 1), in dispc_runtime_resume()
2631 REG_GET(dispc, DSS_SYSSTATUS, 2, 2), in dispc_runtime_resume()
2632 REG_GET(dispc, DSS_SYSSTATUS, 3, 3)); in dispc_runtime_resume()
2634 if (dispc->feat->subrev == DISPC_AM625 || in dispc_runtime_resume()
2635 dispc->feat->subrev == DISPC_AM65X) in dispc_runtime_resume()
2636 dev_dbg(dispc->dev, "OLDI RESETDONE %d,%d,%d\n", in dispc_runtime_resume()
2637 REG_GET(dispc, DSS_SYSSTATUS, 5, 5), in dispc_runtime_resume()
2638 REG_GET(dispc, DSS_SYSSTATUS, 6, 6), in dispc_runtime_resume()
2639 REG_GET(dispc, DSS_SYSSTATUS, 7, 7)); in dispc_runtime_resume()
2641 dev_dbg(dispc->dev, "DISPC IDLE %d\n", in dispc_runtime_resume()
2642 REG_GET(dispc, DSS_SYSSTATUS, 9, 9)); in dispc_runtime_resume()
2644 dispc_initial_config(dispc); in dispc_runtime_resume()
2646 dispc->is_enabled = true; in dispc_runtime_resume()
2648 tidss_irq_resume(dispc->tidss); in dispc_runtime_resume()
2657 tidss->dispc = NULL; in dispc_remove()
2677 struct dispc_device *dispc) in dispc_init_am65x_oldi_io_ctrl() argument
2679 dispc->oldi_io_ctrl = in dispc_init_am65x_oldi_io_ctrl()
2682 if (PTR_ERR(dispc->oldi_io_ctrl) == -ENODEV) { in dispc_init_am65x_oldi_io_ctrl()
2683 dispc->oldi_io_ctrl = NULL; in dispc_init_am65x_oldi_io_ctrl()
2684 } else if (IS_ERR(dispc->oldi_io_ctrl)) { in dispc_init_am65x_oldi_io_ctrl()
2686 __func__, PTR_ERR(dispc->oldi_io_ctrl)); in dispc_init_am65x_oldi_io_ctrl()
2687 return PTR_ERR(dispc->oldi_io_ctrl); in dispc_init_am65x_oldi_io_ctrl()
2692 static void dispc_init_errata(struct dispc_device *dispc) in dispc_init_errata() argument
2700 dispc->errata.i2000 = true; in dispc_init_errata()
2701 dev_info(dispc->dev, "WA for erratum i2000: YUV formats disabled\n"); in dispc_init_errata()
2705 static int dispc_softreset(struct dispc_device *dispc) in dispc_softreset() argument
2711 if (dispc->feat->subrev == DISPC_K2G) in dispc_softreset()
2715 REG_FLD_MOD(dispc, DSS_SYSCONFIG, 1, 1, 1); in dispc_softreset()
2717 ret = readl_poll_timeout(dispc->base_common + DSS_SYSSTATUS, in dispc_softreset()
2720 dev_err(dispc->dev, "failed to reset dispc\n"); in dispc_softreset()
2727 static int dispc_init_hw(struct dispc_device *dispc) in dispc_init_hw() argument
2729 struct device *dev = dispc->dev; in dispc_init_hw()
2738 ret = clk_prepare_enable(dispc->fclk); in dispc_init_hw()
2744 ret = dispc_softreset(dispc); in dispc_init_hw()
2748 clk_disable_unprepare(dispc->fclk); in dispc_init_hw()
2758 clk_disable_unprepare(dispc->fclk); in dispc_init_hw()
2774 struct dispc_device *dispc; in dispc_init() local
2791 dispc = devm_kzalloc(dev, sizeof(*dispc), GFP_KERNEL); in dispc_init()
2792 if (!dispc) in dispc_init()
2795 dispc->tidss = tidss; in dispc_init()
2796 dispc->dev = dev; in dispc_init()
2797 dispc->feat = feat; in dispc_init()
2799 dispc_init_errata(dispc); in dispc_init()
2801 dispc->fourccs = devm_kcalloc(dev, ARRAY_SIZE(dispc_color_formats), in dispc_init()
2802 sizeof(*dispc->fourccs), GFP_KERNEL); in dispc_init()
2803 if (!dispc->fourccs) in dispc_init()
2808 if (dispc->errata.i2000 && in dispc_init()
2812 dispc->fourccs[num_fourccs++] = dispc_color_formats[i].fourcc; in dispc_init()
2815 dispc->num_fourccs = num_fourccs; in dispc_init()
2817 dispc_common_regmap = dispc->feat->common_regs; in dispc_init()
2819 r = dispc_iomap_resource(pdev, dispc->feat->common, in dispc_init()
2820 &dispc->base_common); in dispc_init()
2824 for (i = 0; i < dispc->feat->num_planes; i++) { in dispc_init()
2825 r = dispc_iomap_resource(pdev, dispc->feat->vid_name[i], in dispc_init()
2826 &dispc->base_vid[i]); in dispc_init()
2831 for (i = 0; i < dispc->feat->num_vps; i++) { in dispc_init()
2832 u32 gamma_size = dispc->feat->vp_feat.color.gamma_size; in dispc_init()
2836 r = dispc_iomap_resource(pdev, dispc->feat->ovr_name[i], in dispc_init()
2837 &dispc->base_ovr[i]); in dispc_init()
2841 r = dispc_iomap_resource(pdev, dispc->feat->vp_name[i], in dispc_init()
2842 &dispc->base_vp[i]); in dispc_init()
2846 clk = devm_clk_get(dev, dispc->feat->vpclk_name[i]); in dispc_init()
2849 dispc->feat->vpclk_name[i], PTR_ERR(clk)); in dispc_init()
2852 dispc->vp_clk[i] = clk; in dispc_init()
2859 dispc->vp_data[i].gamma_table = gamma_table; in dispc_init()
2863 r = dispc_init_am65x_oldi_io_ctrl(dev, dispc); in dispc_init()
2868 dispc->fclk = devm_clk_get(dev, "fck"); in dispc_init()
2869 if (IS_ERR(dispc->fclk)) { in dispc_init()
2871 __func__, PTR_ERR(dispc->fclk)); in dispc_init()
2872 return PTR_ERR(dispc->fclk); in dispc_init()
2874 dev_dbg(dev, "DSS fclk %lu Hz\n", clk_get_rate(dispc->fclk)); in dispc_init()
2876 of_property_read_u32(dispc->dev->of_node, "max-memory-bandwidth", in dispc_init()
2877 &dispc->memory_bandwidth_limit); in dispc_init()
2879 r = dispc_init_hw(dispc); in dispc_init()
2883 tidss->dispc = dispc; in dispc_init()