Lines Matching full:ams
3 * Xilinx AMS driver
30 /* AMS registers definitions */
263 * struct ams - This structure contains necessary state for xilinx-ams to operate
277 struct ams { struct
291 static inline void ams_ps_update_reg(struct ams *ams, unsigned int offset, in ams_ps_update_reg() argument
296 val = readl(ams->ps_base + offset); in ams_ps_update_reg()
298 writel(regval, ams->ps_base + offset); in ams_ps_update_reg()
301 static inline void ams_pl_update_reg(struct ams *ams, unsigned int offset, in ams_pl_update_reg() argument
306 val = readl(ams->pl_base + offset); in ams_pl_update_reg()
308 writel(regval, ams->pl_base + offset); in ams_pl_update_reg()
311 static void ams_update_intrmask(struct ams *ams, u64 mask, u64 val) in ams_update_intrmask() argument
315 ams->intr_mask = (ams->intr_mask & ~mask) | (val & mask); in ams_update_intrmask()
317 regval = ~(ams->intr_mask | ams->current_masked_alarm); in ams_update_intrmask()
318 writel(regval, ams->base + AMS_IER_0); in ams_update_intrmask()
320 regval = ~(FIELD_GET(AMS_ISR1_INTR_MASK, ams->intr_mask)); in ams_update_intrmask()
321 writel(regval, ams->base + AMS_IER_1); in ams_update_intrmask()
323 regval = ams->intr_mask | ams->current_masked_alarm; in ams_update_intrmask()
324 writel(regval, ams->base + AMS_IDR_0); in ams_update_intrmask()
326 regval = FIELD_GET(AMS_ISR1_INTR_MASK, ams->intr_mask); in ams_update_intrmask()
327 writel(regval, ams->base + AMS_IDR_1); in ams_update_intrmask()
330 static void ams_disable_all_alarms(struct ams *ams) in ams_disable_all_alarms() argument
333 if (ams->ps_base) { in ams_disable_all_alarms()
334 ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_REGCFG1_ALARM_MASK, in ams_disable_all_alarms()
336 ams_ps_update_reg(ams, AMS_REG_CONFIG3, AMS_REGCFG3_ALARM_MASK, in ams_disable_all_alarms()
341 if (ams->pl_base) { in ams_disable_all_alarms()
342 ams_pl_update_reg(ams, AMS_REG_CONFIG1, AMS_REGCFG1_ALARM_MASK, in ams_disable_all_alarms()
344 ams_pl_update_reg(ams, AMS_REG_CONFIG3, AMS_REGCFG3_ALARM_MASK, in ams_disable_all_alarms()
349 static void ams_update_ps_alarm(struct ams *ams, unsigned long alarm_mask) in ams_update_ps_alarm() argument
360 ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_REGCFG1_ALARM_MASK, cfg); in ams_update_ps_alarm()
364 ams_ps_update_reg(ams, AMS_REG_CONFIG3, AMS_REGCFG3_ALARM_MASK, cfg); in ams_update_ps_alarm()
367 static void ams_update_pl_alarm(struct ams *ams, unsigned long alarm_mask) in ams_update_pl_alarm() argument
381 ams_pl_update_reg(ams, AMS_REG_CONFIG1, AMS_REGCFG1_ALARM_MASK, cfg); in ams_update_pl_alarm()
385 ams_pl_update_reg(ams, AMS_REG_CONFIG3, AMS_REGCFG3_ALARM_MASK, cfg); in ams_update_pl_alarm()
388 static void ams_update_alarm(struct ams *ams, unsigned long alarm_mask) in ams_update_alarm() argument
392 if (ams->ps_base) in ams_update_alarm()
393 ams_update_ps_alarm(ams, alarm_mask); in ams_update_alarm()
395 if (ams->pl_base) in ams_update_alarm()
396 ams_update_pl_alarm(ams, alarm_mask); in ams_update_alarm()
398 spin_lock_irqsave(&ams->intr_lock, flags); in ams_update_alarm()
399 ams_update_intrmask(ams, AMS_ISR0_ALARM_MASK, ~alarm_mask); in ams_update_alarm()
400 spin_unlock_irqrestore(&ams->intr_lock, flags); in ams_update_alarm()
405 struct ams *ams = iio_priv(indio_dev); in ams_enable_channel_sequence() local
420 if (ams->ps_base) { in ams_enable_channel_sequence()
422 ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK, in ams_enable_channel_sequence()
427 writel(regval, ams->ps_base + AMS_REG_SEQ_CH0); in ams_enable_channel_sequence()
430 writel(regval, ams->ps_base + AMS_REG_SEQ_CH2); in ams_enable_channel_sequence()
433 ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK, in ams_enable_channel_sequence()
437 if (ams->pl_base) { in ams_enable_channel_sequence()
439 ams_pl_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK, in ams_enable_channel_sequence()
446 writel(regval, ams->pl_base + AMS_REG_SEQ_CH0); in ams_enable_channel_sequence()
449 writel(regval, ams->pl_base + AMS_REG_SEQ_CH1); in ams_enable_channel_sequence()
452 writel(regval, ams->pl_base + AMS_REG_SEQ_CH2); in ams_enable_channel_sequence()
455 ams_pl_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK, in ams_enable_channel_sequence()
460 static int ams_init_device(struct ams *ams) in ams_init_device() argument
466 /* reset AMS */ in ams_init_device()
467 if (ams->ps_base) { in ams_init_device()
468 writel(AMS_PS_RESET_VALUE, ams->ps_base + AMS_VP_VN); in ams_init_device()
470 ret = readl_poll_timeout(ams->base + AMS_PS_CSTS, reg, (reg & expect), in ams_init_device()
476 ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK, in ams_init_device()
480 if (ams->pl_base) { in ams_init_device()
481 value = readl(ams->base + AMS_PL_CSTS); in ams_init_device()
485 writel(AMS_PL_RESET_VALUE, ams->pl_base + AMS_VP_VN); in ams_init_device()
488 ams_pl_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK, in ams_init_device()
492 ams_disable_all_alarms(ams); in ams_init_device()
495 ams_update_intrmask(ams, AMS_ALARM_MASK, AMS_ALARM_MASK); in ams_init_device()
498 writel(AMS_ISR0_ALARM_MASK, ams->base + AMS_ISR_0); in ams_init_device()
499 writel(AMS_ISR1_ALARM_MASK, ams->base + AMS_ISR_1); in ams_init_device()
504 static int ams_enable_single_channel(struct ams *ams, unsigned int offset) in ams_enable_single_channel() argument
535 ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK, in ams_enable_single_channel()
539 ams_ps_update_reg(ams, AMS_REG_CONFIG0, AMS_CONF0_CHANNEL_NUM_MASK, in ams_enable_single_channel()
543 ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK, in ams_enable_single_channel()
549 static int ams_read_vcc_reg(struct ams *ams, unsigned int offset, u32 *data) in ams_read_vcc_reg() argument
555 ret = ams_enable_single_channel(ams, offset); in ams_read_vcc_reg()
560 writel(expect, ams->base + AMS_ISR_1); in ams_read_vcc_reg()
561 ret = readl_poll_timeout(ams->base + AMS_ISR_1, reg, (reg & expect), in ams_read_vcc_reg()
566 *data = readl(ams->base + offset); in ams_read_vcc_reg()
599 static int ams_get_pl_scale(struct ams *ams, int address) in ams_get_pl_scale() argument
616 regval = readl(ams->pl_base + AMS_REG_CONFIG4); in ams_get_pl_scale()
623 regval = readl(ams->pl_base + AMS_REG_CONFIG4); in ams_get_pl_scale()
630 regval = readl(ams->pl_base + AMS_REG_CONFIG4); in ams_get_pl_scale()
637 regval = readl(ams->pl_base + AMS_REG_CONFIG4); in ams_get_pl_scale()
681 struct ams *ams = iio_priv(indio_dev); in ams_read_raw() local
686 mutex_lock(&ams->lock); in ams_read_raw()
688 ret = ams_read_vcc_reg(ams, chan->address, val); in ams_read_raw()
693 *val = readl(ams->pl_base + chan->address); in ams_read_raw()
695 *val = readl(ams->ps_base + chan->address); in ams_read_raw()
699 mutex_unlock(&ams->lock); in ams_read_raw()
708 *val = ams_get_pl_scale(ams, chan->address); in ams_read_raw()
885 struct ams *ams = iio_priv(indio_dev); in ams_read_event_config() local
887 return !!(ams->alarm_mask & ams_get_alarm_mask(chan->scan_index)); in ams_read_event_config()
896 struct ams *ams = iio_priv(indio_dev); in ams_write_event_config() local
901 mutex_lock(&ams->lock); in ams_write_event_config()
904 ams->alarm_mask |= alarm; in ams_write_event_config()
906 ams->alarm_mask &= ~alarm; in ams_write_event_config()
908 ams_update_alarm(ams, ams->alarm_mask); in ams_write_event_config()
910 mutex_unlock(&ams->lock); in ams_write_event_config()
921 struct ams *ams = iio_priv(indio_dev); in ams_read_event_value() local
924 mutex_lock(&ams->lock); in ams_read_event_value()
927 *val = readl(ams->pl_base + offset); in ams_read_event_value()
929 *val = readl(ams->ps_base + offset); in ams_read_event_value()
931 mutex_unlock(&ams->lock); in ams_read_event_value()
942 struct ams *ams = iio_priv(indio_dev); in ams_write_event_value() local
945 mutex_lock(&ams->lock); in ams_write_event_value()
952 ams_pl_update_reg(ams, offset, in ams_write_event_value()
956 ams_ps_update_reg(ams, offset, in ams_write_event_value()
963 writel(val, ams->pl_base + offset); in ams_write_event_value()
965 writel(val, ams->ps_base + offset); in ams_write_event_value()
967 mutex_unlock(&ams->lock); in ams_write_event_value()
1011 * ams_unmask_worker - ams alarm interrupt unmask worker
1023 struct ams *ams = container_of(work, struct ams, ams_unmask_work.work); in ams_unmask_worker() local
1026 spin_lock_irq(&ams->intr_lock); in ams_unmask_worker()
1028 status = readl(ams->base + AMS_ISR_0); in ams_unmask_worker()
1031 unmask = (ams->current_masked_alarm ^ status) & ams->current_masked_alarm; in ams_unmask_worker()
1034 unmask |= ams->intr_mask; in ams_unmask_worker()
1036 ams->current_masked_alarm &= status; in ams_unmask_worker()
1039 ams->current_masked_alarm &= ~ams->intr_mask; in ams_unmask_worker()
1042 writel(unmask, ams->base + AMS_ISR_0); in ams_unmask_worker()
1044 ams_update_intrmask(ams, ~AMS_ALARM_MASK, ~AMS_ALARM_MASK); in ams_unmask_worker()
1046 spin_unlock_irq(&ams->intr_lock); in ams_unmask_worker()
1049 if (ams->current_masked_alarm) in ams_unmask_worker()
1050 schedule_delayed_work(&ams->ams_unmask_work, in ams_unmask_worker()
1057 struct ams *ams = iio_priv(indio_dev); in ams_irq() local
1060 spin_lock(&ams->intr_lock); in ams_irq()
1062 isr0 = readl(ams->base + AMS_ISR_0); in ams_irq()
1065 isr0 &= ~((ams->intr_mask & AMS_ISR0_ALARM_MASK) | ams->current_masked_alarm); in ams_irq()
1067 spin_unlock(&ams->intr_lock); in ams_irq()
1072 writel(isr0, ams->base + AMS_ISR_0); in ams_irq()
1075 ams->current_masked_alarm |= isr0; in ams_irq()
1076 ams_update_intrmask(ams, ~AMS_ALARM_MASK, ~AMS_ALARM_MASK); in ams_irq()
1080 schedule_delayed_work(&ams->ams_unmask_work, in ams_irq()
1083 spin_unlock(&ams->intr_lock); in ams_irq()
1202 struct ams *ams = data; in ams_iounmap_ps() local
1204 iounmap(ams->ps_base); in ams_iounmap_ps()
1209 struct ams *ams = data; in ams_iounmap_pl() local
1211 iounmap(ams->pl_base); in ams_iounmap_pl()
1219 struct ams *ams = iio_priv(indio_dev); in ams_init_module() local
1223 if (fwnode_device_is_compatible(fwnode, "xlnx,zynqmp-ams-ps")) { in ams_init_module()
1224 ams->ps_base = fwnode_iomap(fwnode, 0); in ams_init_module()
1225 if (!ams->ps_base) in ams_init_module()
1227 ret = devm_add_action_or_reset(dev, ams_iounmap_ps, ams); in ams_init_module()
1234 } else if (fwnode_device_is_compatible(fwnode, "xlnx,zynqmp-ams-pl")) { in ams_init_module()
1235 ams->pl_base = fwnode_iomap(fwnode, 0); in ams_init_module()
1236 if (!ams->pl_base) in ams_init_module()
1239 ret = devm_add_action_or_reset(dev, ams_iounmap_pl, ams); in ams_init_module()
1248 } else if (fwnode_device_is_compatible(fwnode, "xlnx,zynqmp-ams")) { in ams_init_module()
1249 /* add AMS channels to iio device channels */ in ams_init_module()
1261 struct ams *ams = iio_priv(indio_dev); in ams_parse_firmware() local
1311 ams->pl_base + falling_off); in ams_parse_firmware()
1313 ams->pl_base + rising_off); in ams_parse_firmware()
1316 ams->ps_base + falling_off); in ams_parse_firmware()
1318 ams->ps_base + rising_off); in ams_parse_firmware()
1343 { .compatible = "xlnx,zynqmp-ams" },
1351 struct ams *ams; in ams_probe() local
1355 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*ams)); in ams_probe()
1359 ams = iio_priv(indio_dev); in ams_probe()
1360 mutex_init(&ams->lock); in ams_probe()
1361 spin_lock_init(&ams->intr_lock); in ams_probe()
1363 indio_dev->name = "xilinx-ams"; in ams_probe()
1368 ams->base = devm_platform_ioremap_resource(pdev, 0); in ams_probe()
1369 if (IS_ERR(ams->base)) in ams_probe()
1370 return PTR_ERR(ams->base); in ams_probe()
1372 ams->clk = devm_clk_get_enabled(&pdev->dev, NULL); in ams_probe()
1373 if (IS_ERR(ams->clk)) in ams_probe()
1374 return PTR_ERR(ams->clk); in ams_probe()
1376 ret = devm_delayed_work_autocancel(&pdev->dev, &ams->ams_unmask_work, in ams_probe()
1385 ret = ams_init_device(ams); in ams_probe()
1387 return dev_err_probe(&pdev->dev, ret, "failed to initialize AMS\n"); in ams_probe()
1395 ret = devm_request_irq(&pdev->dev, irq, &ams_irq, 0, "ams-irq", in ams_probe()
1407 struct ams *ams = iio_priv(dev_get_drvdata(dev)); in ams_suspend() local
1409 clk_disable_unprepare(ams->clk); in ams_suspend()
1416 struct ams *ams = iio_priv(dev_get_drvdata(dev)); in ams_resume() local
1418 return clk_prepare_enable(ams->clk); in ams_resume()
1426 .name = "xilinx-ams",