Lines Matching +full:0 +full:- +full:64
1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/mtd/spi-nor.h>
12 #define USE_FSR BIT(0)
14 #define SPINOR_OP_RDFSR 0x70 /* Read flag status register */
15 #define SPINOR_OP_CLFSR 0x50 /* Clear flag status register */
16 #define SPINOR_OP_MT_DTR_RD 0xfd /* Fast Read opcode in DTR mode */
17 #define SPINOR_OP_MT_RD_ANY_REG 0x85 /* Read volatile register */
18 #define SPINOR_OP_MT_WR_ANY_REG 0x81 /* Write volatile register */
19 #define SPINOR_REG_MT_CFR0V 0x00 /* For setting octal DTR mode */
20 #define SPINOR_REG_MT_CFR1V 0x01 /* For setting dummy cycles */
21 #define SPINOR_REG_MT_CFR1V_DEF 0x1f /* Default dummy cycles */
22 #define SPINOR_MT_OCT_DTR 0xe7 /* Enable Octal DTR. */
23 #define SPINOR_MT_EXSPI 0xff /* Enable Extended SPI (default) */
26 #define FSR_READY BIT(7) /* Device status, 0 = Busy, 1 = Ready */
33 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MT_WR_ANY_REG, 0), \
34 SPI_MEM_OP_ADDR(naddr, addr, 0), \
36 SPI_MEM_OP_DATA_OUT(ndata, buf, 0))
39 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDFSR, 0), \
42 SPI_MEM_OP_DATA_IN(1, buf, 0))
45 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLFSR, 0), \
53 u8 *buf = nor->bouncebuf; in micron_st_nor_octal_dtr_en()
55 u8 addr_mode_nbytes = nor->params->addr_mode_nbytes; in micron_st_nor_octal_dtr_en()
62 ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto); in micron_st_nor_octal_dtr_en()
66 buf[0] = SPINOR_MT_OCT_DTR; in micron_st_nor_octal_dtr_en()
70 ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto); in micron_st_nor_octal_dtr_en()
75 ret = spi_nor_read_id(nor, 0, 8, buf, SNOR_PROTO_8_8_8_DTR); in micron_st_nor_octal_dtr_en()
77 dev_dbg(nor->dev, "error %d reading JEDEC ID after enabling 8D-8D-8D mode\n", ret); in micron_st_nor_octal_dtr_en()
81 if (memcmp(buf, nor->info->id, nor->info->id_len)) in micron_st_nor_octal_dtr_en()
82 return -EINVAL; in micron_st_nor_octal_dtr_en()
84 return 0; in micron_st_nor_octal_dtr_en()
90 u8 *buf = nor->bouncebuf; in micron_st_nor_octal_dtr_dis()
94 * The register is 1-byte wide, but 1-byte transactions are not allowed in micron_st_nor_octal_dtr_dis()
95 * in 8D-8D-8D mode. The next register is the dummy cycle configuration in micron_st_nor_octal_dtr_dis()
98 * because the value was changed when enabling 8D-8D-8D mode, it should in micron_st_nor_octal_dtr_dis()
101 buf[0] = SPINOR_MT_EXSPI; in micron_st_nor_octal_dtr_dis()
104 MICRON_ST_NOR_WR_ANY_REG_OP(nor->addr_nbytes, in micron_st_nor_octal_dtr_dis()
111 ret = spi_nor_read_id(nor, 0, 0, buf, SNOR_PROTO_1_1_1); in micron_st_nor_octal_dtr_dis()
113 dev_dbg(nor->dev, "error %d reading JEDEC ID after disabling 8D-8D-8D mode\n", ret); in micron_st_nor_octal_dtr_dis()
117 if (memcmp(buf, nor->info->id, nor->info->id_len)) in micron_st_nor_octal_dtr_dis()
118 return -EINVAL; in micron_st_nor_octal_dtr_dis()
120 return 0; in micron_st_nor_octal_dtr_dis()
131 nor->params->set_octal_dtr = micron_st_nor_set_octal_dtr; in mt35xu512aba_default_init()
137 nor->params->hwcaps.mask |= SNOR_HWCAPS_READ_8_8_8_DTR; in mt35xu512aba_post_sfdp_fixup()
138 spi_nor_set_read_settings(&nor->params->reads[SNOR_CMD_READ_8_8_8_DTR], in mt35xu512aba_post_sfdp_fixup()
139 0, 20, SPINOR_OP_MT_DTR_RD, in mt35xu512aba_post_sfdp_fixup()
142 nor->cmd_ext_type = SPI_NOR_EXT_REPEAT; in mt35xu512aba_post_sfdp_fixup()
143 nor->params->rdsr_dummy = 8; in mt35xu512aba_post_sfdp_fixup()
144 nor->params->rdsr_addr_nbytes = 0; in mt35xu512aba_post_sfdp_fixup()
151 nor->params->quad_enable = NULL; in mt35xu512aba_post_sfdp_fixup()
153 return 0; in mt35xu512aba_post_sfdp_fixup()
162 { "mt35xu512aba", INFO(0x2c5b1a, 0, 128 * 1024, 512)
169 { "mt35xu02g", INFO(0x2c5b1c, 0, 128 * 1024, 2048)
177 { "n25q016a", INFO(0x20bb15, 0, 64 * 1024, 32)
179 { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64)
181 { "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64)
183 { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128)
185 { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128)
187 { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256)
193 { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256)
199 { "mt25ql256a", INFO6(0x20ba19, 0x104400, 64 * 1024, 512)
204 { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512)
209 { "mt25qu256a", INFO6(0x20bb19, 0x104400, 64 * 1024, 512)
216 { "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512)
220 { "mt25ql512a", INFO6(0x20ba20, 0x104400, 64 * 1024, 1024)
225 { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024)
231 { "mt25qu512a", INFO6(0x20bb20, 0x104400, 64 * 1024, 1024)
236 { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024)
242 { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048)
248 { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048)
253 { "mt25ql02g", INFO(0x20ba22, 0, 64 * 1024, 4096)
258 { "mt25qu02g", INFO(0x20bb22, 0, 64 * 1024, 4096)
265 { "m25p05", INFO(0x202010, 0, 32 * 1024, 2) },
266 { "m25p10", INFO(0x202011, 0, 32 * 1024, 4) },
267 { "m25p20", INFO(0x202012, 0, 64 * 1024, 4) },
268 { "m25p40", INFO(0x202013, 0, 64 * 1024, 8) },
269 { "m25p80", INFO(0x202014, 0, 64 * 1024, 16) },
270 { "m25p16", INFO(0x202015, 0, 64 * 1024, 32) },
271 { "m25p32", INFO(0x202016, 0, 64 * 1024, 64) },
272 { "m25p64", INFO(0x202017, 0, 64 * 1024, 128) },
273 { "m25p128", INFO(0x202018, 0, 256 * 1024, 64) },
275 { "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2) },
276 { "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4) },
277 { "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4) },
278 { "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8) },
279 { "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16) },
280 { "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32) },
281 { "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64) },
282 { "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128) },
283 { "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64) },
285 { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2) },
286 { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16) },
287 { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32) },
289 { "m25pe20", INFO(0x208012, 0, 64 * 1024, 4) },
290 { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16) },
291 { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32)
294 { "m25px16", INFO(0x207115, 0, 64 * 1024, 32)
296 { "m25px32", INFO(0x207116, 0, 64 * 1024, 64)
298 { "m25px32-s0", INFO(0x207316, 0, 64 * 1024, 64)
300 { "m25px32-s1", INFO(0x206316, 0, 64 * 1024, 64)
302 { "m25px64", INFO(0x207117, 0, 64 * 1024, 128) },
303 { "m25px80", INFO(0x207114, 0, 64 * 1024, 16) },
307 * micron_st_nor_read_fsr() - Read the Flag Status Register.
309 * @fsr: pointer to a DMA-able buffer where the value of the
313 * Return: 0 on success, -errno otherwise.
319 if (nor->spimem) { in micron_st_nor_read_fsr()
322 if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) { in micron_st_nor_read_fsr()
323 op.addr.nbytes = nor->params->rdsr_addr_nbytes; in micron_st_nor_read_fsr()
324 op.dummy.nbytes = nor->params->rdsr_dummy; in micron_st_nor_read_fsr()
332 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); in micron_st_nor_read_fsr()
334 ret = spi_mem_exec_op(nor->spimem, &op); in micron_st_nor_read_fsr()
341 dev_dbg(nor->dev, "error %d reading FSR\n", ret); in micron_st_nor_read_fsr()
347 * micron_st_nor_clear_fsr() - Clear the Flag Status Register.
354 if (nor->spimem) { in micron_st_nor_clear_fsr()
357 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); in micron_st_nor_clear_fsr()
359 ret = spi_mem_exec_op(nor->spimem, &op); in micron_st_nor_clear_fsr()
362 NULL, 0); in micron_st_nor_clear_fsr()
366 dev_dbg(nor->dev, "error %d clearing FSR\n", ret); in micron_st_nor_clear_fsr()
370 * micron_st_nor_ready() - Query the Status Register as well as the Flag Status
375 * Return: 1 if ready, 0 if not ready, -errno on errors.
382 if (sr_ready < 0) in micron_st_nor_ready()
385 ret = micron_st_nor_read_fsr(nor, nor->bouncebuf); in micron_st_nor_ready()
394 return ret == -EOPNOTSUPP ? sr_ready : ret; in micron_st_nor_ready()
397 if (nor->bouncebuf[0] & (FSR_E_ERR | FSR_P_ERR)) { in micron_st_nor_ready()
398 if (nor->bouncebuf[0] & FSR_E_ERR) in micron_st_nor_ready()
399 dev_err(nor->dev, "Erase operation failed.\n"); in micron_st_nor_ready()
401 dev_err(nor->dev, "Program operation failed.\n"); in micron_st_nor_ready()
403 if (nor->bouncebuf[0] & FSR_PT_ERR) in micron_st_nor_ready()
404 dev_err(nor->dev, in micron_st_nor_ready()
419 return -EIO; in micron_st_nor_ready()
422 return sr_ready && !!(nor->bouncebuf[0] & FSR_READY); in micron_st_nor_ready()
427 nor->flags |= SNOR_F_HAS_LOCK; in micron_st_nor_default_init()
428 nor->flags &= ~SNOR_F_HAS_16BIT_SR; in micron_st_nor_default_init()
429 nor->params->quad_enable = NULL; in micron_st_nor_default_init()
434 struct spi_nor_flash_parameter *params = nor->params; in micron_st_nor_late_init()
436 if (nor->info->mfr_flags & USE_FSR) in micron_st_nor_late_init()
437 params->ready = micron_st_nor_ready; in micron_st_nor_late_init()
439 if (!params->set_4byte_addr_mode) in micron_st_nor_late_init()
440 params->set_4byte_addr_mode = spi_nor_set_4byte_addr_mode_wren_en4b_ex4b; in micron_st_nor_late_init()
442 return 0; in micron_st_nor_late_init()