Lines Matching +full:256 +full:- +full:byte
1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/mtd/spi-nor.h>
67 * struct spansion_nor_params - Spansion private parameters.
76 * spansion_nor_clear_sr() - Clear the Status Register.
81 const struct spansion_nor_params *priv_params = nor->params->priv; in spansion_nor_clear_sr()
84 if (nor->spimem) { in spansion_nor_clear_sr()
85 struct spi_mem_op op = SPANSION_OP(priv_params->clsr); in spansion_nor_clear_sr()
87 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); in spansion_nor_clear_sr()
89 ret = spi_mem_exec_op(nor->spimem, &op); in spansion_nor_clear_sr()
96 dev_dbg(nor->dev, "error %d clearing SR\n", ret); in spansion_nor_clear_sr()
101 struct spi_nor_flash_parameter *params = nor->params; in cypress_nor_sr_ready_and_clear_reg()
103 CYPRESS_NOR_RD_ANY_REG_OP(params->addr_mode_nbytes, addr, in cypress_nor_sr_ready_and_clear_reg()
104 0, nor->bouncebuf); in cypress_nor_sr_ready_and_clear_reg()
107 if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) { in cypress_nor_sr_ready_and_clear_reg()
108 op.dummy.nbytes = params->rdsr_dummy; in cypress_nor_sr_ready_and_clear_reg()
112 ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto); in cypress_nor_sr_ready_and_clear_reg()
116 if (nor->bouncebuf[0] & (SR_E_ERR | SR_P_ERR)) { in cypress_nor_sr_ready_and_clear_reg()
117 if (nor->bouncebuf[0] & SR_E_ERR) in cypress_nor_sr_ready_and_clear_reg()
118 dev_err(nor->dev, "Erase Error occurred\n"); in cypress_nor_sr_ready_and_clear_reg()
120 dev_err(nor->dev, "Programming Error occurred\n"); in cypress_nor_sr_ready_and_clear_reg()
128 return -EIO; in cypress_nor_sr_ready_and_clear_reg()
131 return !(nor->bouncebuf[0] & SR_WIP); in cypress_nor_sr_ready_and_clear_reg()
134 * cypress_nor_sr_ready_and_clear() - Query the Status Register of each die by
139 * Return: 1 if ready, 0 if not ready, -errno on errors.
143 struct spi_nor_flash_parameter *params = nor->params; in cypress_nor_sr_ready_and_clear()
148 for (i = 0; i < params->n_dice; i++) { in cypress_nor_sr_ready_and_clear()
149 addr = params->vreg_offset[i] + SPINOR_REG_CYPRESS_STR1; in cypress_nor_sr_ready_and_clear()
163 u8 *buf = nor->bouncebuf; in cypress_nor_set_memlat()
165 u8 addr_mode_nbytes = nor->params->addr_mode_nbytes; in cypress_nor_set_memlat()
170 ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto); in cypress_nor_set_memlat()
181 ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto); in cypress_nor_set_memlat()
185 nor->read_dummy = 24; in cypress_nor_set_memlat()
193 u8 *buf = nor->bouncebuf; in cypress_nor_set_octal_dtr_bits()
198 CYPRESS_NOR_WR_ANY_REG_OP(nor->params->addr_mode_nbytes, in cypress_nor_set_octal_dtr_bits()
201 return spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto); in cypress_nor_set_octal_dtr_bits()
206 const struct spi_nor_flash_parameter *params = nor->params; in cypress_nor_octal_dtr_en()
207 u8 *buf = nor->bouncebuf; in cypress_nor_octal_dtr_en()
211 for (i = 0; i < params->n_dice; i++) { in cypress_nor_octal_dtr_en()
212 addr = params->vreg_offset[i] + SPINOR_REG_CYPRESS_CFR2; in cypress_nor_octal_dtr_en()
217 addr = params->vreg_offset[i] + SPINOR_REG_CYPRESS_CFR5; in cypress_nor_octal_dtr_en()
224 ret = spi_nor_read_id(nor, nor->addr_nbytes, 3, buf, in cypress_nor_octal_dtr_en()
227 dev_dbg(nor->dev, "error %d reading JEDEC ID after enabling 8D-8D-8D mode\n", ret); in cypress_nor_octal_dtr_en()
231 if (memcmp(buf, nor->info->id, nor->info->id_len)) in cypress_nor_octal_dtr_en()
232 return -EINVAL; in cypress_nor_octal_dtr_en()
240 u8 *buf = nor->bouncebuf; in cypress_nor_set_single_spi_bits()
243 * The register is 1-byte wide, but 1-byte transactions are not allowed in cypress_nor_set_single_spi_bits()
244 * in 8D-8D-8D mode. Since there is no register at the next location, in cypress_nor_set_single_spi_bits()
250 CYPRESS_NOR_WR_ANY_REG_OP(nor->addr_nbytes, addr, 2, buf); in cypress_nor_set_single_spi_bits()
256 const struct spi_nor_flash_parameter *params = nor->params; in cypress_nor_octal_dtr_dis()
257 u8 *buf = nor->bouncebuf; in cypress_nor_octal_dtr_dis()
261 for (i = 0; i < params->n_dice; i++) { in cypress_nor_octal_dtr_dis()
262 addr = params->vreg_offset[i] + SPINOR_REG_CYPRESS_CFR5; in cypress_nor_octal_dtr_dis()
271 dev_dbg(nor->dev, "error %d reading JEDEC ID after disabling 8D-8D-8D mode\n", ret); in cypress_nor_octal_dtr_dis()
275 if (memcmp(buf, nor->info->id, nor->info->id_len)) in cypress_nor_octal_dtr_dis()
276 return -EINVAL; in cypress_nor_octal_dtr_dis()
284 u8 addr_mode_nbytes = nor->params->addr_mode_nbytes; in cypress_nor_quad_enable_volatile_reg()
290 nor->bouncebuf); in cypress_nor_quad_enable_volatile_reg()
292 ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto); in cypress_nor_quad_enable_volatile_reg()
296 if (nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR1_QUAD_EN) in cypress_nor_quad_enable_volatile_reg()
300 nor->bouncebuf[0] |= SPINOR_REG_CYPRESS_CFR1_QUAD_EN; in cypress_nor_quad_enable_volatile_reg()
303 nor->bouncebuf); in cypress_nor_quad_enable_volatile_reg()
304 ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto); in cypress_nor_quad_enable_volatile_reg()
308 cfr1v_written = nor->bouncebuf[0]; in cypress_nor_quad_enable_volatile_reg()
313 nor->bouncebuf); in cypress_nor_quad_enable_volatile_reg()
314 ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto); in cypress_nor_quad_enable_volatile_reg()
318 if (nor->bouncebuf[0] != cfr1v_written) { in cypress_nor_quad_enable_volatile_reg()
319 dev_err(nor->dev, "CFR1: Read back test failed\n"); in cypress_nor_quad_enable_volatile_reg()
320 return -EIO; in cypress_nor_quad_enable_volatile_reg()
327 * cypress_nor_quad_enable_volatile() - enable Quad I/O mode in volatile
332 * to a risk of the non-volatile registers corruption by power interrupt. This
334 * bit in the CFR1 non-volatile in advance (typically by a Flash programmer
336 * also set during Flash power-up.
338 * Return: 0 on success, -errno otherwise.
342 struct spi_nor_flash_parameter *params = nor->params; in cypress_nor_quad_enable_volatile()
347 for (i = 0; i < params->n_dice; i++) { in cypress_nor_quad_enable_volatile()
348 addr = params->vreg_offset[i] + SPINOR_REG_CYPRESS_CFR1; in cypress_nor_quad_enable_volatile()
358 * cypress_nor_determine_addr_mode_by_sr1() - Determine current address mode
359 * (3 or 4-byte) by querying status
366 * from RDSR1(no address), RDAR(3-byte address), and RDAR(4-byte address).
368 * Return: 0 on success, -errno otherwise.
375 nor->bouncebuf); in cypress_nor_determine_addr_mode_by_sr1()
379 ret = spi_nor_read_sr(nor, &nor->bouncebuf[1]); in cypress_nor_determine_addr_mode_by_sr1()
383 ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto); in cypress_nor_determine_addr_mode_by_sr1()
387 is3byte = (nor->bouncebuf[0] == nor->bouncebuf[1]); in cypress_nor_determine_addr_mode_by_sr1()
391 nor->bouncebuf); in cypress_nor_determine_addr_mode_by_sr1()
392 ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto); in cypress_nor_determine_addr_mode_by_sr1()
396 is4byte = (nor->bouncebuf[0] == nor->bouncebuf[1]); in cypress_nor_determine_addr_mode_by_sr1()
399 return -EIO; in cypress_nor_determine_addr_mode_by_sr1()
409 * cypress_nor_set_addr_mode_nbytes() - Set the number of address bytes mode of
414 * query CFR2V[7] to confirm. If determination is failed, force enter to 4-byte
417 * Return: 0 on success, -errno otherwise.
426 * Read SR1 by RDSR1 and RDAR(3- AND 4-byte addr). Use write enable in cypress_nor_set_addr_mode_nbytes()
427 * that sets bit-1 in SR1. in cypress_nor_set_addr_mode_nbytes()
449 0, nor->bouncebuf); in cypress_nor_set_addr_mode_nbytes()
450 ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto); in cypress_nor_set_addr_mode_nbytes()
454 if (nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR2_ADRBYT) { in cypress_nor_set_addr_mode_nbytes()
462 nor->params->addr_nbytes = addr_mode; in cypress_nor_set_addr_mode_nbytes()
463 nor->params->addr_mode_nbytes = addr_mode; in cypress_nor_set_addr_mode_nbytes()
469 * cypress_nor_get_page_size() - Get flash page size configuration.
472 * The BFPT table advertises a 512B or 256B page size depending on part but the
473 * page size is actually configurable (with the default being 256B). Read from
476 * Return: 0 on success, -errno otherwise.
481 CYPRESS_NOR_RD_ANY_REG_OP(nor->params->addr_mode_nbytes, in cypress_nor_get_page_size()
482 0, 0, nor->bouncebuf); in cypress_nor_get_page_size()
483 struct spi_nor_flash_parameter *params = nor->params; in cypress_nor_get_page_size()
488 * Use the minimum common page size configuration. Programming 256-byte in cypress_nor_get_page_size()
489 * under 512-byte page size configuration is safe. in cypress_nor_get_page_size()
491 params->page_size = 256; in cypress_nor_get_page_size()
492 for (i = 0; i < params->n_dice; i++) { in cypress_nor_get_page_size()
493 op.addr.val = params->vreg_offset[i] + SPINOR_REG_CYPRESS_CFR3; in cypress_nor_get_page_size()
495 ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto); in cypress_nor_get_page_size()
499 if (!(nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR3_PGSZ)) in cypress_nor_get_page_size()
503 params->page_size = 512; in cypress_nor_get_page_size()
511 * Programming is supported only in 16-byte ECC data unit granularity. in cypress_nor_ecc_init()
512 * Byte-programming, bit-walking, or multiple program operations to the in cypress_nor_ecc_init()
515 nor->params->writesize = 16; in cypress_nor_ecc_init()
516 nor->flags |= SNOR_F_ECC; in cypress_nor_ecc_init()
533 CYPRESS_NOR_RD_ANY_REG_OP(nor->params->addr_mode_nbytes, in s25fs256t_post_bfpt_fixup()
535 nor->bouncebuf); in s25fs256t_post_bfpt_fixup()
536 ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto); in s25fs256t_post_bfpt_fixup()
541 if (nor->bouncebuf[0]) in s25fs256t_post_bfpt_fixup()
542 return -ENODEV; in s25fs256t_post_bfpt_fixup()
549 struct spi_nor_flash_parameter *params = nor->params; in s25fs256t_post_sfdp_fixup()
556 params->vreg_offset = devm_kmalloc(nor->dev, sizeof(u32), GFP_KERNEL); in s25fs256t_post_sfdp_fixup()
557 if (!params->vreg_offset) in s25fs256t_post_sfdp_fixup()
558 return -ENOMEM; in s25fs256t_post_sfdp_fixup()
560 params->vreg_offset[0] = SPINOR_REG_CYPRESS_VREG; in s25fs256t_post_sfdp_fixup()
561 params->n_dice = 1; in s25fs256t_post_sfdp_fixup()
564 params->hwcaps.mask |= SNOR_HWCAPS_PP_1_1_4; in s25fs256t_post_sfdp_fixup()
565 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_1_1_4], in s25fs256t_post_sfdp_fixup()
597 nor->params->quad_enable = cypress_nor_quad_enable_volatile; in s25hx_t_post_bfpt_fixup()
604 struct spi_nor_flash_parameter *params = nor->params; in s25hx_t_post_sfdp_fixup()
605 struct spi_nor_erase_type *erase_type = params->erase_map.erase_type; in s25hx_t_post_sfdp_fixup()
608 if (!params->n_dice || !params->vreg_offset) { in s25hx_t_post_sfdp_fixup()
609 dev_err(nor->dev, "%s failed. The volatile register offset could not be retrieved from SFDP.\n", in s25hx_t_post_sfdp_fixup()
611 return -EOPNOTSUPP; in s25hx_t_post_sfdp_fixup()
615 if (params->size == SZ_256M) in s25hx_t_post_sfdp_fixup()
616 params->n_dice = 2; in s25hx_t_post_sfdp_fixup()
619 * In some parts, 3byte erase opcodes are advertised by 4BAIT. in s25hx_t_post_sfdp_fixup()
620 * Convert them to 4byte erase opcodes. in s25hx_t_post_sfdp_fixup()
640 struct spi_nor_flash_parameter *params = nor->params; in s25hx_t_late_init()
643 params->reads[SNOR_CMD_READ_FAST].num_mode_clocks = 8; in s25hx_t_late_init()
644 params->ready = cypress_nor_sr_ready_and_clear; in s25hx_t_late_init()
657 * cypress_nor_set_octal_dtr() - Enable or disable octal DTR on Cypress flashes.
664 * Return: 0 on success, -errno otherwise.
674 struct spi_nor_flash_parameter *params = nor->params; in s28hx_t_post_sfdp_fixup()
676 if (!params->n_dice || !params->vreg_offset) { in s28hx_t_post_sfdp_fixup()
677 dev_err(nor->dev, "%s failed. The volatile register offset could not be retrieved from SFDP.\n", in s28hx_t_post_sfdp_fixup()
679 return -EOPNOTSUPP; in s28hx_t_post_sfdp_fixup()
683 if (params->size == SZ_256M) in s28hx_t_post_sfdp_fixup()
684 params->n_dice = 2; in s28hx_t_post_sfdp_fixup()
688 * 8D-8D-8D Fast Read opcode as 0x00. But it actually should be 0xEE. in s28hx_t_post_sfdp_fixup()
690 if (params->reads[SNOR_CMD_READ_8_8_8_DTR].opcode == 0) in s28hx_t_post_sfdp_fixup()
691 params->reads[SNOR_CMD_READ_8_8_8_DTR].opcode = in s28hx_t_post_sfdp_fixup()
694 /* This flash is also missing the 4-byte Page Program opcode bit. */ in s28hx_t_post_sfdp_fixup()
695 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP], in s28hx_t_post_sfdp_fixup()
701 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_8_8_8_DTR], in s28hx_t_post_sfdp_fixup()
709 params->rdsr_addr_nbytes = 4; in s28hx_t_post_sfdp_fixup()
723 struct spi_nor_flash_parameter *params = nor->params; in s28hx_t_late_init()
725 params->set_octal_dtr = cypress_nor_set_octal_dtr; in s28hx_t_late_init()
726 params->ready = cypress_nor_sr_ready_and_clear; in s28hx_t_late_init()
744 * The S25FS-S chip family reports 512-byte pages in BFPT but in s25fs_s_nor_post_bfpt_fixups()
746 * of 256 bytes. Overwrite the page size advertised by BFPT in s25fs_s_nor_post_bfpt_fixups()
749 nor->params->page_size = 256; in s25fs_s_nor_post_bfpt_fixups()
759 /* Spansion/Cypress -- single (large) sector size only, at least
766 { "s25fl128s0", INFO6(0x012018, 0x4d0080, 256 * 1024, 64)
770 { "s25fl128s1", INFO6(0x012018, 0x4d0180, 64 * 1024, 256)
774 { "s25fl256s0", INFO6(0x010219, 0x4d0080, 256 * 1024, 128)
783 { "s25fl512s", INFO6(0x010220, 0x4d0080, 256 * 1024, 256)
788 { "s25fs128s1", INFO6(0x012018, 0x4d0181, 64 * 1024, 256)
792 { "s25fs256s0", INFO6(0x010219, 0x4d0081, 256 * 1024, 128)
800 { "s25fs512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 256)
804 { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64) },
805 { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256) },
806 { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64)
810 { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256)
845 { "s25fl128l", INFO(0x016018, 0, 64 * 1024, 256)
911 * spansion_nor_sr_ready_and_clear() - Query the Status Register to see if the
915 * Return: 1 if ready, 0 if not ready, -errno on errors.
921 ret = spi_nor_read_sr(nor, nor->bouncebuf); in spansion_nor_sr_ready_and_clear()
925 if (nor->bouncebuf[0] & (SR_E_ERR | SR_P_ERR)) { in spansion_nor_sr_ready_and_clear()
926 if (nor->bouncebuf[0] & SR_E_ERR) in spansion_nor_sr_ready_and_clear()
927 dev_err(nor->dev, "Erase Error occurred\n"); in spansion_nor_sr_ready_and_clear()
929 dev_err(nor->dev, "Programming Error occurred\n"); in spansion_nor_sr_ready_and_clear()
943 return -EIO; in spansion_nor_sr_ready_and_clear()
946 return !(nor->bouncebuf[0] & SR_WIP); in spansion_nor_sr_ready_and_clear()
951 struct spi_nor_flash_parameter *params = nor->params; in spansion_nor_late_init()
953 u8 mfr_flags = nor->info->mfr_flags; in spansion_nor_late_init()
955 if (params->size > SZ_16M) { in spansion_nor_late_init()
956 nor->flags |= SNOR_F_4B_OPCODES; in spansion_nor_late_init()
957 /* No small sector erase for 4-byte command set */ in spansion_nor_late_init()
958 nor->erase_opcode = SPINOR_OP_SE; in spansion_nor_late_init()
959 nor->mtd.erasesize = nor->info->sector_size; in spansion_nor_late_init()
963 priv_params = devm_kmalloc(nor->dev, sizeof(*priv_params), in spansion_nor_late_init()
966 return -ENOMEM; in spansion_nor_late_init()
969 priv_params->clsr = SPINOR_OP_CLSR; in spansion_nor_late_init()
971 priv_params->clsr = SPINOR_OP_CLPEF; in spansion_nor_late_init()
973 params->priv = priv_params; in spansion_nor_late_init()
974 params->ready = spansion_nor_sr_ready_and_clear; in spansion_nor_late_init()