35 #define KVASER_PCIEFD_VENDOR 0x1a07
37 #define KVASER_PCIEFD_4HS_DEVICE_ID 0x000d
38 #define KVASER_PCIEFD_2HS_V2_DEVICE_ID 0x000e
39 #define KVASER_PCIEFD_HS_V2_DEVICE_ID 0x000f
40 #define KVASER_PCIEFD_MINIPCIE_HS_V2_DEVICE_ID 0x0010
41 #define KVASER_PCIEFD_MINIPCIE_2HS_V2_DEVICE_ID 0x0011
44 #define KVASER_PCIEFD_2CAN_V3_DEVICE_ID 0x0012
45 #define KVASER_PCIEFD_1CAN_V3_DEVICE_ID 0x0013
46 #define KVASER_PCIEFD_4CAN_V2_DEVICE_ID 0x0014
47 #define KVASER_PCIEFD_MINIPCIE_2CAN_V3_DEVICE_ID 0x0015
48 #define KVASER_PCIEFD_MINIPCIE_1CAN_V3_DEVICE_ID 0x0016
51 #define KVASER_PCIEFD_ALTERA_DMA_64BIT BIT(0)
57 #define KVASER_PCIEFD_KCAN_FIFO_REG 0x100
58 #define KVASER_PCIEFD_KCAN_FIFO_LAST_REG 0x180
59 #define KVASER_PCIEFD_KCAN_CTRL_REG 0x2c0
60 #define KVASER_PCIEFD_KCAN_CMD_REG 0x400
61 #define KVASER_PCIEFD_KCAN_IEN_REG 0x408
62 #define KVASER_PCIEFD_KCAN_IRQ_REG 0x410
63 #define KVASER_PCIEFD_KCAN_TX_NR_PACKETS_REG 0x414
64 #define KVASER_PCIEFD_KCAN_STAT_REG 0x418
65 #define KVASER_PCIEFD_KCAN_MODE_REG 0x41c
66 #define KVASER_PCIEFD_KCAN_BTRN_REG 0x420
67 #define KVASER_PCIEFD_KCAN_BUS_LOAD_REG 0x424
68 #define KVASER_PCIEFD_KCAN_BTRD_REG 0x428
69 #define KVASER_PCIEFD_KCAN_PWM_REG 0x430
71 #define KVASER_PCIEFD_SYSID_VERSION_REG 0x8
72 #define KVASER_PCIEFD_SYSID_CANFREQ_REG 0xc
73 #define KVASER_PCIEFD_SYSID_BUSFREQ_REG 0x10
74 #define KVASER_PCIEFD_SYSID_BUILD_REG 0x14
76 #define KVASER_PCIEFD_SRB_FIFO_LAST_REG 0x1f4
78 #define KVASER_PCIEFD_SRB_CMD_REG 0x0
79 #define KVASER_PCIEFD_SRB_IEN_REG 0x04
80 #define KVASER_PCIEFD_SRB_IRQ_REG 0x0c
81 #define KVASER_PCIEFD_SRB_STAT_REG 0x10
82 #define KVASER_PCIEFD_SRB_RX_NR_PACKETS_REG 0x14
83 #define KVASER_PCIEFD_SRB_CTRL_REG 0x18
88 #define KVASER_PCIEFD_SYSID_VERSION_MINOR_MASK GENMASK(7, 0)
91 /* Reset DMA buffer 0, 1 and FIFO offset */
94 #define KVASER_PCIEFD_SRB_CMD_FOR BIT(0)
96 /* DMA underflow, buffer 0 and 1 */
99 /* DMA overflow, buffer 0 and 1 */
102 /* DMA packet done, buffer 0 and 1 */
112 #define KVASER_PCIEFD_SRB_RX_NR_PACKETS_MASK GENMASK(7, 0)
115 #define KVASER_PCIEFD_SRB_CTRL_DMA_ENABLE BIT(0)
119 #define KVASER_PCIEFD_KCAN_CTRL_TYPE_EFLUSH 0x4
120 #define KVASER_PCIEFD_KCAN_CTRL_TYPE_EFRAME 0x5
125 #define KVASER_PCIEFD_KCAN_CMD_MASK GENMASK(5, 0)
129 #define KVASER_PCIEFD_KCAN_CMD_SRQ BIT(0)
150 #define KVASER_PCIEFD_KCAN_IRQ_TAR BIT(0)
155 #define KVASER_PCIEFD_KCAN_TX_NR_PACKETS_CURRENT_MASK GENMASK(7, 0)
197 #define KVASER_PCIEFD_KCAN_BTRN_BRP_MASK GENMASK(12, 0)
201 #define KVASER_PCIEFD_KCAN_PWM_TRIGGER_MASK GENMASK(7, 0)
204 #define KVASER_PCIEFD_PACK_TYPE_DATA 0x0
205 #define KVASER_PCIEFD_PACK_TYPE_ACK 0x1
206 #define KVASER_PCIEFD_PACK_TYPE_TXRQ 0x2
207 #define KVASER_PCIEFD_PACK_TYPE_ERROR 0x3
208 #define KVASER_PCIEFD_PACK_TYPE_EFLUSH_ACK 0x4
209 #define KVASER_PCIEFD_PACK_TYPE_EFRAME_ACK 0x5
210 #define KVASER_PCIEFD_PACK_TYPE_ACK_DATA 0x6
211 #define KVASER_PCIEFD_PACK_TYPE_STATUS 0x8
212 #define KVASER_PCIEFD_PACK_TYPE_BUS_LOAD 0x9
217 #define KVASER_PCIEFD_PACKET_SEQ_MASK GENMASK(7, 0)
222 #define KVASER_PCIEFD_RPACKET_ID_MASK GENMASK(28, 0)
244 #define KVASER_PCIEFD_SPACK_TXERR_MASK GENMASK(7, 0)
251 #define KVASER_PCIEFD_EPACK_DIR_TX BIT(0)
315 	.serdes = 0x1000,
316 	.pci_ien = 0x50,
317 	.pci_irq = 0x40,
318 	.sysid = 0x1f020,
319 	.loopback = 0x1f000,
320 	.kcan_srb_fifo = 0x1f200,
321 	.kcan_srb = 0x1f400,
322 	.kcan_ch0 = 0x10000,
323 	.kcan_ch1 = 0x11000,
327 	.serdes = 0x280c8,
328 	.pci_ien = 0x102004,
329 	.pci_irq = 0x102008,
330 	.sysid = 0x100000,
331 	.loopback = 0x103000,
332 	.kcan_srb_fifo = 0x120000,
333 	.kcan_srb = 0x121000,
334 	.kcan_ch0 = 0x140000,
335 	.kcan_ch1 = 0x142000,
340 	.kcan_tx = { BIT(0), BIT(1), BIT(2), BIT(3) },
341 	.all = GENMASK(4, 0),
460 		0,
566 	iowrite32(GENMASK(31, 0), can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);  in kvaser_pciefd_start_controller_flush()
600 	iowrite32(0, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);  in kvaser_pciefd_bus_on()
601 	iowrite32(GENMASK(31, 0), can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);  in kvaser_pciefd_bus_on()
615 	iowrite32(0, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);  in kvaser_pciefd_bus_on()
616 	iowrite32(GENMASK(31, 0), can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);  in kvaser_pciefd_bus_on()
622 	can->bec.txerr = 0;  in kvaser_pciefd_bus_on()
623 	can->bec.rxerr = 0;  in kvaser_pciefd_bus_on()
624 	can->err_rep_cnt = 0;  in kvaser_pciefd_bus_on()
626 	return 0;  in kvaser_pciefd_bus_on()
682 	return 0;  in kvaser_pciefd_open()
688 	int ret = 0;  in kvaser_pciefd_stop()
699 		iowrite32(0, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);  in kvaser_pciefd_stop()
716 	memset(p, 0, sizeof(*p));  in kvaser_pciefd_prepare_tx_packet()
721 		p->header[0] |= KVASER_PCIEFD_RPACKET_RTR;  in kvaser_pciefd_prepare_tx_packet()
724 		p->header[0] |= KVASER_PCIEFD_RPACKET_IDE;  in kvaser_pciefd_prepare_tx_packet()
726 	p->header[0] |= FIELD_PREP(KVASER_PCIEFD_RPACKET_ID_MASK, cf->can_id);  in kvaser_pciefd_prepare_tx_packet()
767 	can_put_echo_skb(skb, netdev, can->echo_idx, 0);  in kvaser_pciefd_start_xmit()
773 	iowrite32(packet.header[0],  in kvaser_pciefd_start_xmit()
790 		__raw_writel(0, can->reg_base +  in kvaser_pciefd_start_xmit()
831 				 test, test & KVASER_PCIEFD_KCAN_MODE_RM, 0, 10);  in kvaser_pciefd_set_bittiming()
845 	return 0;  in kvaser_pciefd_set_bittiming()
861 	int ret = 0;  in kvaser_pciefd_set_mode()
883 	return 0;  in kvaser_pciefd_get_berr_counter()
892 	can->err_rep_cnt = 0;  in kvaser_pciefd_bec_poll_timer()
911 	for (i = 0; i < pcie->nr_channels; i++) {  in kvaser_pciefd_setup_can_ctrls()
926 		can->cmd_seq = 0;  in kvaser_pciefd_setup_can_ctrls()
927 		can->err_rep_cnt = 0;  in kvaser_pciefd_setup_can_ctrls()
928 		can->bec.txerr = 0;  in kvaser_pciefd_setup_can_ctrls()
929 		can->bec.rxerr = 0;  in kvaser_pciefd_setup_can_ctrls()
933 		timer_setup(&can->bec_poll_timer, kvaser_pciefd_bec_poll_timer, 0);  in kvaser_pciefd_setup_can_ctrls()
936 		iowrite32(0, can->reg_base + KVASER_PCIEFD_KCAN_BUS_LOAD_REG);  in kvaser_pciefd_setup_can_ctrls()
944 		can->echo_idx = 0;  in kvaser_pciefd_setup_can_ctrls()
974 		iowrite32(GENMASK(31, 0), can->reg_base + KVASER_PCIEFD_KCAN_IRQ_REG);  in kvaser_pciefd_setup_can_ctrls()
982 	return 0;  in kvaser_pciefd_setup_can_ctrls()
989 	for (i = 0; i < pcie->nr_channels; i++) {  in kvaser_pciefd_reg_candev()
996 			for (j = 0; j < i; j++)  in kvaser_pciefd_reg_candev()
1002 	return 0;  in kvaser_pciefd_reg_candev()
1016 	word2 = 0;  in kvaser_pciefd_write_dma_map_altera()
1018 	serdes_base = KVASER_PCIEFD_SERDES_ADDR(pcie) + 0x8 * index;  in kvaser_pciefd_write_dma_map_altera()
1020 	iowrite32(word2, serdes_base + 0x4);  in kvaser_pciefd_write_dma_map_altera()
1028 	u32 msb = 0x0;  in kvaser_pciefd_write_dma_map_sf2()
1033 	serdes_base = KVASER_PCIEFD_SERDES_ADDR(pcie) + 0x10 * index;  in kvaser_pciefd_write_dma_map_sf2()
1035 	iowrite32(msb, serdes_base + 0x4);  in kvaser_pciefd_write_dma_map_sf2()
1046 	iowrite32(0, KVASER_PCIEFD_SRB_ADDR(pcie) + KVASER_PCIEFD_SRB_CTRL_REG);  in kvaser_pciefd_setup_dma()
1047 	for (i = 0; i < KVASER_PCIEFD_DMA_COUNT; i++) {  in kvaser_pciefd_setup_dma()
1086 	return 0;  in kvaser_pciefd_setup_dma()
1112 	if (pcie->freq_to_ticks_div == 0)  in kvaser_pciefd_setup_board()
1115 	iowrite32(0, KVASER_PCIEFD_LOOPBACK_ADDR(pcie));  in kvaser_pciefd_setup_board()
1117 	return 0;  in kvaser_pciefd_setup_board()
1157 	cf->can_id = FIELD_GET(KVASER_PCIEFD_RPACKET_ID_MASK, p->header[0]);  in kvaser_pciefd_handle_data_packet()
1158 	if (p->header[0] & KVASER_PCIEFD_RPACKET_IDE)  in kvaser_pciefd_handle_data_packet()
1161 	if (p->header[0] & KVASER_PCIEFD_RPACKET_RTR) {  in kvaser_pciefd_handle_data_packet()
1202 	if (p->header[0] & KVASER_PCIEFD_SPACK_BOFF ||  in kvaser_pciefd_packet_to_state()
1203 	    p->header[0] & KVASER_PCIEFD_SPACK_IRM)  in kvaser_pciefd_packet_to_state()
1218 	*tx_state = bec->txerr >= bec->rxerr ? *new_state : 0;  in kvaser_pciefd_packet_to_state()
1219 	*rx_state = bec->txerr <= bec->rxerr ? *new_state : 0;  in kvaser_pciefd_packet_to_state()
1233 	bec.txerr = FIELD_GET(KVASER_PCIEFD_SPACK_TXERR_MASK, p->header[0]);  in kvaser_pciefd_rx_error_frame()
1234 	bec.rxerr = FIELD_GET(KVASER_PCIEFD_SPACK_RXERR_MASK, p->header[0]);  in kvaser_pciefd_rx_error_frame()
1271 	return 0;  in kvaser_pciefd_rx_error_frame()
1291 	return 0;  in kvaser_pciefd_handle_error_packet()
1302 	bec.txerr = FIELD_GET(KVASER_PCIEFD_SPACK_TXERR_MASK, p->header[0]);  in kvaser_pciefd_handle_status_resp()
1303 	bec.rxerr = FIELD_GET(KVASER_PCIEFD_SPACK_RXERR_MASK, p->header[0]);  in kvaser_pciefd_handle_status_resp()
1338 	return 0;  in kvaser_pciefd_handle_status_resp()
1358 	if (p->header[0] & KVASER_PCIEFD_SPACK_IRM &&  in kvaser_pciefd_handle_status_packet()
1359 	    p->header[0] & KVASER_PCIEFD_SPACK_RMCD &&  in kvaser_pciefd_handle_status_packet()
1366 	} else if (p->header[0] & KVASER_PCIEFD_SPACK_IDET &&  in kvaser_pciefd_handle_status_packet()
1367 		   p->header[0] & KVASER_PCIEFD_SPACK_IRM &&  in kvaser_pciefd_handle_status_packet()
1387 	} else if (p->header[0] & KVASER_PCIEFD_SPACK_RMCD &&  in kvaser_pciefd_handle_status_packet()
1394 	return 0;  in kvaser_pciefd_handle_status_packet()
1405 	if (p->header[0] & KVASER_PCIEFD_APACKET_ABL) {  in kvaser_pciefd_handle_nack_packet()
1435 	if (p->header[0] & KVASER_PCIEFD_APACKET_CT)  in kvaser_pciefd_handle_ack_packet()
1436 		return 0;  in kvaser_pciefd_handle_ack_packet()
1438 	if (p->header[0] & KVASER_PCIEFD_APACKET_NACK) {  in kvaser_pciefd_handle_ack_packet()
1443 	if (p->header[0] & KVASER_PCIEFD_APACKET_FLU) {  in kvaser_pciefd_handle_ack_packet()
1446 		int echo_idx = FIELD_GET(KVASER_PCIEFD_PACKET_SEQ_MASK, p->header[0]);  in kvaser_pciefd_handle_ack_packet()
1467 	return 0;  in kvaser_pciefd_handle_ack_packet()
1484 	return 0;  in kvaser_pciefd_handle_eflush_packet()
1497 	int ret = 0;  in kvaser_pciefd_read_packet()
1501 		*start_pos = 0;  in kvaser_pciefd_read_packet()
1502 		return 0;  in kvaser_pciefd_read_packet()
1505 	p->header[0] = le32_to_cpu(buffer[pos++]);  in kvaser_pciefd_read_packet()
1517 		if (!(p->header[0] & KVASER_PCIEFD_RPACKET_RTR)) {  in kvaser_pciefd_read_packet()
1547 			 "Received unexpected packet type 0x%08X\n", type);  in kvaser_pciefd_read_packet()
1551 		dev_err(&pcie->pci->dev, "Unknown packet type 0x%08X\n", type);  in kvaser_pciefd_read_packet()
1573 	int pos = 0;  in kvaser_pciefd_read_buffer()
1574 	int res = 0;  in kvaser_pciefd_read_buffer()
1578 	} while (!res && pos > 0 && pos < KVASER_PCIEFD_DMA_SIZE);  in kvaser_pciefd_read_buffer()
1588 		kvaser_pciefd_read_buffer(pcie, 0);  in kvaser_pciefd_receive_irq()
1589 		/* Reset DMA buffer 0 */  in kvaser_pciefd_receive_irq()
1605 		dev_err(&pcie->pci->dev, "DMA IRQ error 0x%08X\n", irq);  in kvaser_pciefd_receive_irq()
1643 	for (i = 0; i < pcie->nr_channels; i++) {  in kvaser_pciefd_irq_handler()
1662 	for (i = 0; i < pcie->nr_channels; i++) {  in kvaser_pciefd_teardown_can_ctrls()
1666 			iowrite32(0, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);  in kvaser_pciefd_teardown_can_ctrls()
1698 	pcie->reg_base = pci_iomap(pdev, 0, 0);  in kvaser_pciefd_probe()
1744 	return 0;  in kvaser_pciefd_probe()
1748 	iowrite32(0, irq_en_base);  in kvaser_pciefd_probe()
1753 	iowrite32(0, KVASER_PCIEFD_SRB_ADDR(pcie) + KVASER_PCIEFD_SRB_CTRL_REG);  in kvaser_pciefd_probe()
1772 	for (i = 0; i < pcie->nr_channels; i++) {  in kvaser_pciefd_remove_all_ctrls()
1776 			iowrite32(0, can->reg_base + KVASER_PCIEFD_KCAN_IEN_REG);  in kvaser_pciefd_remove_all_ctrls()
1792 	iowrite32(0, KVASER_PCIEFD_SRB_ADDR(pcie) + KVASER_PCIEFD_SRB_CTRL_REG);  in kvaser_pciefd_remove()
1793 	iowrite32(0, KVASER_PCIEFD_PCI_IEN_ADDR(pcie));  in kvaser_pciefd_remove()