35 #define MTK_PHY_TXVLD_DA_RG			0x12
73 #define   MTK_PHY_DA_RX_PSBN_GBE_MASK		GENMASK(6, 4)
106 #define   MTK_PHY_CR_TX_AMP_OFFSET_B_MASK	GENMASK(6, 0)
110 #define   MTK_PHY_CR_TX_AMP_OFFSET_D_MASK	GENMASK(6, 0)
215 #define   MTK_PHY_LED_ON_MASK			GENMASK(6, 0)
222 #define   MTK_PHY_LED_ON_FORCE_ON		BIT(6)
234 #define   MTK_PHY_LED_BLINK_COLLISION		BIT(6)
250 #define EFS_DA_TX_I2MPB_B(x)			(((x) >> 6) & GENMASK(5, 0))
256 #define EFS_DA_TX_AMP_OFFSET_C(x)		(((x) >> 6) & GENMASK(5, 0))
262 #define EFS_DA_TX_R50_D(x)			(((x) >> 6) & GENMASK(5, 0))
408 	const int vals_9481[16] = { 10, 6, 6, 10,  in tx_amp_fill_result()
409 				    10, 6, 6, 10,  in tx_amp_fill_result()
410 				    10, 6, 6, 10,  in tx_amp_fill_result()
411 				    10, 6, 6, 10 };  in tx_amp_fill_result()
447 		       MTK_PHY_DA_TX_I2MPB_B_HBT_MASK, (buf[1] + bias[6]) << 8);  in tx_amp_fill_result()
710 	__phy_write(phydev, 0x12, 0xc);  in mt798x_phy_common_finetune()
715 	__phy_write(phydev, 0x12, 0xe);  in mt798x_phy_common_finetune()
720 	__phy_write(phydev, 0x12, 0x0);  in mt798x_phy_common_finetune()
725 	__phy_write(phydev, 0x12, 0x0);  in mt798x_phy_common_finetune()
730 	__phy_write(phydev, 0x12, 0x0);  in mt798x_phy_common_finetune()
734 	/* SSTrKf100 = 6 */  in mt798x_phy_common_finetune()
736 	/* SSTrKf1000Mas = 6 */  in mt798x_phy_common_finetune()
738 	/* SSTrKf1000Slv = 6 */  in mt798x_phy_common_finetune()
740 	__phy_write(phydev, 0x12, 0x2e);  in mt798x_phy_common_finetune()
764 	/* ResetSyncOffset = 6 */  in mt7981_phy_finetune()
766 	__phy_write(phydev, 0x12, 0x0);  in mt7981_phy_finetune()
771 	__phy_write(phydev, 0x12, 0x3e);  in mt7981_phy_finetune()
778 	__phy_write(phydev, 0x12, 0x34);  in mt7981_phy_finetune()
783 	__phy_write(phydev, 0x12, 0x55);  in mt7981_phy_finetune()
837 	__phy_write(phydev, 0x12, 0x0);  in mt7988_phy_finetune()
842 	/* MrvlTrFix100Kp = 6, MrvlTrFix100Kf = 7,  in mt7988_phy_finetune()
843 	 * MrvlTrFix1000Kp = 6, MrvlTrFix1000Kf = 7  in mt7988_phy_finetune()
846 	__phy_write(phydev, 0x12, 0x6f);  in mt7988_phy_finetune()
851 	__phy_write(phydev, 0x12, 0xc3);  in mt7988_phy_finetune()
930 	__phy_write(phydev, 0x12, 0x0);  in mt798x_phy_eee()
935 	__phy_write(phydev, 0x12, 0x2);  in mt798x_phy_eee()
938 	/* RegEEE_slv_wake_tr_timer_tar = 6, RegEEE_slv_remtx_timer_tar = 20 */  in mt798x_phy_eee()
940 	__phy_write(phydev, 0x12, 0x0);  in mt798x_phy_eee()
945 	__phy_write(phydev, 0x12, 0x0);  in mt798x_phy_eee()
950 	__phy_write(phydev, 0x12, 0x0);  in mt798x_phy_eee()
955 	__phy_write(phydev, 0x12, 0x0);  in mt798x_phy_eee()
960 	__phy_write(phydev, 0x12, 0x0);  in mt798x_phy_eee()
965 	__phy_write(phydev, 0x12, 0x0);  in mt798x_phy_eee()