37 /* PARF registers */
232 	void __iomem *parf;			/* DT parf */  member
350 	writel(1, pcie->parf + PARF_PHY_CTRL);  in qcom_pcie_deinit_2_1_0()
395 	val = readl(pcie->parf + PARF_PHY_CTRL);  in qcom_pcie_post_init_2_1_0()
397 	writel(val, pcie->parf + PARF_PHY_CTRL);  in qcom_pcie_post_init_2_1_0()
408 		       pcie->parf + PARF_PCS_DEEMPH);  in qcom_pcie_post_init_2_1_0()
411 		       pcie->parf + PARF_PCS_SWING);  in qcom_pcie_post_init_2_1_0()
412 		writel(PHY_RX0_EQ(4), pcie->parf + PARF_CONFIG_BITS);  in qcom_pcie_post_init_2_1_0()
417 		val = readl(pcie->parf + PARF_PHY_CTRL);  in qcom_pcie_post_init_2_1_0()
420 		writel(val, pcie->parf + PARF_PHY_CTRL);  in qcom_pcie_post_init_2_1_0()
424 	val = readl(pcie->parf + PARF_PHY_REFCLK);  in qcom_pcie_post_init_2_1_0()
429 	writel(val, pcie->parf + PARF_PHY_REFCLK);  in qcom_pcie_post_init_2_1_0()
516 	writel(0, pcie->parf + PARF_DBI_BASE_ADDR);  in qcom_pcie_post_init_1_0_0()
519 		u32 val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT);  in qcom_pcie_post_init_1_0_0()
522 		writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT);  in qcom_pcie_post_init_1_0_0()
535 	val = readl(pcie->parf + PARF_LTSSM);  in qcom_pcie_2_3_2_ltssm_enable()
537 	writel(val, pcie->parf + PARF_LTSSM);  in qcom_pcie_2_3_2_ltssm_enable()
602 	val = readl(pcie->parf + PARF_PHY_CTRL);  in qcom_pcie_post_init_2_3_2()
604 	writel(val, pcie->parf + PARF_PHY_CTRL);  in qcom_pcie_post_init_2_3_2()
607 	writel(0, pcie->parf + PARF_DBI_BASE_ADDR);  in qcom_pcie_post_init_2_3_2()
610 	val = readl(pcie->parf + PARF_SYS_CTRL);  in qcom_pcie_post_init_2_3_2()
612 	writel(val, pcie->parf + PARF_SYS_CTRL);  in qcom_pcie_post_init_2_3_2()
614 	val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);  in qcom_pcie_post_init_2_3_2()
616 	writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);  in qcom_pcie_post_init_2_3_2()
618 	val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);  in qcom_pcie_post_init_2_3_2()
620 	writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);  in qcom_pcie_post_init_2_3_2()
656 	res->resets[9].id = "parf";  in qcom_pcie_get_resources_2_4_0()
799 	writel(SLV_ADDR_SPACE_SZ, pcie->parf + PARF_SLV_ADDR_SPACE_SIZE);  in qcom_pcie_post_init_2_3_3()
801 	val = readl(pcie->parf + PARF_PHY_CTRL);  in qcom_pcie_post_init_2_3_3()
803 	writel(val, pcie->parf + PARF_PHY_CTRL);  in qcom_pcie_post_init_2_3_3()
805 	writel(0, pcie->parf + PARF_DBI_BASE_ADDR);  in qcom_pcie_post_init_2_3_3()
810 		pcie->parf + PARF_SYS_CTRL);  in qcom_pcie_post_init_2_3_3()
811 	writel(0, pcie->parf + PARF_Q2A_FLUSH);  in qcom_pcie_post_init_2_3_3()
921 	writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE);  in qcom_pcie_init_2_7_0()
924 	val = readl(pcie->parf + PARF_PHY_CTRL);  in qcom_pcie_init_2_7_0()
926 	writel(val, pcie->parf + PARF_PHY_CTRL);  in qcom_pcie_init_2_7_0()
929 	writel(0, pcie->parf + PARF_DBI_BASE_ADDR);  in qcom_pcie_init_2_7_0()
932 	val = readl(pcie->parf + PARF_SYS_CTRL);  in qcom_pcie_init_2_7_0()
934 	writel(val, pcie->parf + PARF_SYS_CTRL);  in qcom_pcie_init_2_7_0()
936 	val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);  in qcom_pcie_init_2_7_0()
938 	writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);  in qcom_pcie_init_2_7_0()
941 	val = readl(pcie->parf + PARF_PM_CTRL);  in qcom_pcie_init_2_7_0()
943 	writel(val, pcie->parf + PARF_PM_CTRL);  in qcom_pcie_init_2_7_0()
945 	val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);  in qcom_pcie_init_2_7_0()
947 	writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);  in qcom_pcie_init_2_7_0()
983 	void __iomem *bdf_to_sid_base = pcie->parf + PARF_BDF_TO_SID_TABLE_N;  in qcom_pcie_config_sid_1_9_0()
1112 		pcie->parf + PARF_SLV_ADDR_SPACE_SIZE);  in qcom_pcie_post_init_2_9_0()
1114 	val = readl(pcie->parf + PARF_PHY_CTRL);  in qcom_pcie_post_init_2_9_0()
1116 	writel(val, pcie->parf + PARF_PHY_CTRL);  in qcom_pcie_post_init_2_9_0()
1118 	writel(0, pcie->parf + PARF_DBI_BASE_ADDR);  in qcom_pcie_post_init_2_9_0()
1120 	writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE);  in qcom_pcie_post_init_2_9_0()
1122 		pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);  in qcom_pcie_post_init_2_9_0()
1130 		pcie->parf + PARF_SYS_CTRL);  in qcom_pcie_post_init_2_9_0()
1132 	writel(0, pcie->parf + PARF_Q2A_FLUSH);  in qcom_pcie_post_init_2_9_0()
1148 		writel(0, pcie->parf + PARF_BDF_TO_SID_TABLE_N + (4 * i));  in qcom_pcie_post_init_2_9_0()
1480 	pcie->parf = devm_platform_ioremap_resource_byname(pdev, "parf");  in qcom_pcie_probe()
1481 	if (IS_ERR(pcie->parf)) {  in qcom_pcie_probe()
1482 		ret = PTR_ERR(pcie->parf);  in qcom_pcie_probe()