Lines Matching +full:pcie +full:- +full:4
1 // SPDX-License-Identifier: GPL-2.0
3 * Qualcomm PCIe root complex driver
5 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
8 * Author: Stanimir Varbanov <svarbanov@mm-sol.com>
27 #include <linux/phy/pcie.h>
35 #include "pcie-designware.h"
78 #define AUX_PWR_DET BIT(4)
112 #define BYPASS BIT(4)
150 #define QCOM_PCIE_1_0_0_MAX_CLOCKS 4
167 #define QCOM_PCIE_2_3_2_MAX_CLOCKS 4
181 #define QCOM_PCIE_2_4_0_MAX_CLOCKS 4
218 int (*get_resources)(struct qcom_pcie *pcie);
219 int (*init)(struct qcom_pcie *pcie);
220 int (*post_init)(struct qcom_pcie *pcie);
221 void (*deinit)(struct qcom_pcie *pcie);
222 void (*ltssm_enable)(struct qcom_pcie *pcie);
223 int (*config_sid)(struct qcom_pcie *pcie);
244 #define to_qcom_pcie(x) dev_get_drvdata((x)->dev)
246 static void qcom_ep_reset_assert(struct qcom_pcie *pcie) in qcom_ep_reset_assert() argument
248 gpiod_set_value_cansleep(pcie->reset, 1); in qcom_ep_reset_assert()
252 static void qcom_ep_reset_deassert(struct qcom_pcie *pcie) in qcom_ep_reset_deassert() argument
256 gpiod_set_value_cansleep(pcie->reset, 0); in qcom_ep_reset_deassert()
262 struct qcom_pcie *pcie = to_qcom_pcie(pci); in qcom_pcie_start_link() local
265 if (pcie->cfg->ops->ltssm_enable) in qcom_pcie_start_link()
266 pcie->cfg->ops->ltssm_enable(pcie); in qcom_pcie_start_link()
278 val = readl(pci->dbi_base + offset + PCI_EXP_SLTCAP); in qcom_pcie_clear_hpc()
280 writel(val, pci->dbi_base + offset + PCI_EXP_SLTCAP); in qcom_pcie_clear_hpc()
285 static void qcom_pcie_2_1_0_ltssm_enable(struct qcom_pcie *pcie) in qcom_pcie_2_1_0_ltssm_enable() argument
290 val = readl(pcie->elbi + ELBI_SYS_CTRL); in qcom_pcie_2_1_0_ltssm_enable()
292 writel(val, pcie->elbi + ELBI_SYS_CTRL); in qcom_pcie_2_1_0_ltssm_enable()
295 static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie) in qcom_pcie_get_resources_2_1_0() argument
297 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; in qcom_pcie_get_resources_2_1_0()
298 struct dw_pcie *pci = pcie->pci; in qcom_pcie_get_resources_2_1_0()
299 struct device *dev = pci->dev; in qcom_pcie_get_resources_2_1_0()
300 bool is_apq = of_device_is_compatible(dev->of_node, "qcom,pcie-apq8064"); in qcom_pcie_get_resources_2_1_0()
303 res->supplies[0].supply = "vdda"; in qcom_pcie_get_resources_2_1_0()
304 res->supplies[1].supply = "vdda_phy"; in qcom_pcie_get_resources_2_1_0()
305 res->supplies[2].supply = "vdda_refclk"; in qcom_pcie_get_resources_2_1_0()
306 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies), in qcom_pcie_get_resources_2_1_0()
307 res->supplies); in qcom_pcie_get_resources_2_1_0()
311 res->clks[0].id = "iface"; in qcom_pcie_get_resources_2_1_0()
312 res->clks[1].id = "core"; in qcom_pcie_get_resources_2_1_0()
313 res->clks[2].id = "phy"; in qcom_pcie_get_resources_2_1_0()
314 res->clks[3].id = "aux"; in qcom_pcie_get_resources_2_1_0()
315 res->clks[4].id = "ref"; in qcom_pcie_get_resources_2_1_0()
318 ret = devm_clk_bulk_get(dev, 3, res->clks); in qcom_pcie_get_resources_2_1_0()
323 ret = devm_clk_bulk_get_optional(dev, 2, res->clks + 3); in qcom_pcie_get_resources_2_1_0()
327 res->resets[0].id = "pci"; in qcom_pcie_get_resources_2_1_0()
328 res->resets[1].id = "axi"; in qcom_pcie_get_resources_2_1_0()
329 res->resets[2].id = "ahb"; in qcom_pcie_get_resources_2_1_0()
330 res->resets[3].id = "por"; in qcom_pcie_get_resources_2_1_0()
331 res->resets[4].id = "phy"; in qcom_pcie_get_resources_2_1_0()
332 res->resets[5].id = "ext"; in qcom_pcie_get_resources_2_1_0()
335 res->num_resets = is_apq ? 5 : 6; in qcom_pcie_get_resources_2_1_0()
336 ret = devm_reset_control_bulk_get_exclusive(dev, res->num_resets, res->resets); in qcom_pcie_get_resources_2_1_0()
343 static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie) in qcom_pcie_deinit_2_1_0() argument
345 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; in qcom_pcie_deinit_2_1_0()
347 clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); in qcom_pcie_deinit_2_1_0()
348 reset_control_bulk_assert(res->num_resets, res->resets); in qcom_pcie_deinit_2_1_0()
350 writel(1, pcie->parf + PARF_PHY_CTRL); in qcom_pcie_deinit_2_1_0()
352 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); in qcom_pcie_deinit_2_1_0()
355 static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) in qcom_pcie_init_2_1_0() argument
357 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; in qcom_pcie_init_2_1_0()
358 struct dw_pcie *pci = pcie->pci; in qcom_pcie_init_2_1_0()
359 struct device *dev = pci->dev; in qcom_pcie_init_2_1_0()
362 /* reset the PCIe interface as uboot can leave it undefined state */ in qcom_pcie_init_2_1_0()
363 ret = reset_control_bulk_assert(res->num_resets, res->resets); in qcom_pcie_init_2_1_0()
369 ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies); in qcom_pcie_init_2_1_0()
375 ret = reset_control_bulk_deassert(res->num_resets, res->resets); in qcom_pcie_init_2_1_0()
378 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); in qcom_pcie_init_2_1_0()
385 static int qcom_pcie_post_init_2_1_0(struct qcom_pcie *pcie) in qcom_pcie_post_init_2_1_0() argument
387 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; in qcom_pcie_post_init_2_1_0()
388 struct dw_pcie *pci = pcie->pci; in qcom_pcie_post_init_2_1_0()
389 struct device *dev = pci->dev; in qcom_pcie_post_init_2_1_0()
390 struct device_node *node = dev->of_node; in qcom_pcie_post_init_2_1_0()
394 /* enable PCIe clocks and resets */ in qcom_pcie_post_init_2_1_0()
395 val = readl(pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_1_0()
397 writel(val, pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_1_0()
399 ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); in qcom_pcie_post_init_2_1_0()
403 if (of_device_is_compatible(node, "qcom,pcie-ipq8064") || in qcom_pcie_post_init_2_1_0()
404 of_device_is_compatible(node, "qcom,pcie-ipq8064-v2")) { in qcom_pcie_post_init_2_1_0()
408 pcie->parf + PARF_PCS_DEEMPH); in qcom_pcie_post_init_2_1_0()
411 pcie->parf + PARF_PCS_SWING); in qcom_pcie_post_init_2_1_0()
412 writel(PHY_RX0_EQ(4), pcie->parf + PARF_CONFIG_BITS); in qcom_pcie_post_init_2_1_0()
415 if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) { in qcom_pcie_post_init_2_1_0()
417 val = readl(pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_1_0()
420 writel(val, pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_1_0()
424 val = readl(pcie->parf + PARF_PHY_REFCLK); in qcom_pcie_post_init_2_1_0()
426 if (!of_device_is_compatible(node, "qcom,pcie-apq8064")) in qcom_pcie_post_init_2_1_0()
429 writel(val, pcie->parf + PARF_PHY_REFCLK); in qcom_pcie_post_init_2_1_0()
434 /* Set the Max TLP size to 2K, instead of using default of 4K */ in qcom_pcie_post_init_2_1_0()
436 pci->dbi_base + AXI_MSTR_RESP_COMP_CTRL0); in qcom_pcie_post_init_2_1_0()
438 pci->dbi_base + AXI_MSTR_RESP_COMP_CTRL1); in qcom_pcie_post_init_2_1_0()
440 qcom_pcie_clear_hpc(pcie->pci); in qcom_pcie_post_init_2_1_0()
445 static int qcom_pcie_get_resources_1_0_0(struct qcom_pcie *pcie) in qcom_pcie_get_resources_1_0_0() argument
447 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0; in qcom_pcie_get_resources_1_0_0()
448 struct dw_pcie *pci = pcie->pci; in qcom_pcie_get_resources_1_0_0()
449 struct device *dev = pci->dev; in qcom_pcie_get_resources_1_0_0()
452 res->vdda = devm_regulator_get(dev, "vdda"); in qcom_pcie_get_resources_1_0_0()
453 if (IS_ERR(res->vdda)) in qcom_pcie_get_resources_1_0_0()
454 return PTR_ERR(res->vdda); in qcom_pcie_get_resources_1_0_0()
456 res->clks[0].id = "iface"; in qcom_pcie_get_resources_1_0_0()
457 res->clks[1].id = "aux"; in qcom_pcie_get_resources_1_0_0()
458 res->clks[2].id = "master_bus"; in qcom_pcie_get_resources_1_0_0()
459 res->clks[3].id = "slave_bus"; in qcom_pcie_get_resources_1_0_0()
461 ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks); in qcom_pcie_get_resources_1_0_0()
465 res->core = devm_reset_control_get_exclusive(dev, "core"); in qcom_pcie_get_resources_1_0_0()
466 return PTR_ERR_OR_ZERO(res->core); in qcom_pcie_get_resources_1_0_0()
469 static void qcom_pcie_deinit_1_0_0(struct qcom_pcie *pcie) in qcom_pcie_deinit_1_0_0() argument
471 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0; in qcom_pcie_deinit_1_0_0()
473 reset_control_assert(res->core); in qcom_pcie_deinit_1_0_0()
474 clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); in qcom_pcie_deinit_1_0_0()
475 regulator_disable(res->vdda); in qcom_pcie_deinit_1_0_0()
478 static int qcom_pcie_init_1_0_0(struct qcom_pcie *pcie) in qcom_pcie_init_1_0_0() argument
480 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0; in qcom_pcie_init_1_0_0()
481 struct dw_pcie *pci = pcie->pci; in qcom_pcie_init_1_0_0()
482 struct device *dev = pci->dev; in qcom_pcie_init_1_0_0()
485 ret = reset_control_deassert(res->core); in qcom_pcie_init_1_0_0()
491 ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); in qcom_pcie_init_1_0_0()
497 ret = regulator_enable(res->vdda); in qcom_pcie_init_1_0_0()
506 clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); in qcom_pcie_init_1_0_0()
508 reset_control_assert(res->core); in qcom_pcie_init_1_0_0()
513 static int qcom_pcie_post_init_1_0_0(struct qcom_pcie *pcie) in qcom_pcie_post_init_1_0_0() argument
516 writel(0, pcie->parf + PARF_DBI_BASE_ADDR); in qcom_pcie_post_init_1_0_0()
519 u32 val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT); in qcom_pcie_post_init_1_0_0()
522 writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT); in qcom_pcie_post_init_1_0_0()
525 qcom_pcie_clear_hpc(pcie->pci); in qcom_pcie_post_init_1_0_0()
530 static void qcom_pcie_2_3_2_ltssm_enable(struct qcom_pcie *pcie) in qcom_pcie_2_3_2_ltssm_enable() argument
535 val = readl(pcie->parf + PARF_LTSSM); in qcom_pcie_2_3_2_ltssm_enable()
537 writel(val, pcie->parf + PARF_LTSSM); in qcom_pcie_2_3_2_ltssm_enable()
540 static int qcom_pcie_get_resources_2_3_2(struct qcom_pcie *pcie) in qcom_pcie_get_resources_2_3_2() argument
542 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2; in qcom_pcie_get_resources_2_3_2()
543 struct dw_pcie *pci = pcie->pci; in qcom_pcie_get_resources_2_3_2()
544 struct device *dev = pci->dev; in qcom_pcie_get_resources_2_3_2()
547 res->supplies[0].supply = "vdda"; in qcom_pcie_get_resources_2_3_2()
548 res->supplies[1].supply = "vddpe-3v3"; in qcom_pcie_get_resources_2_3_2()
549 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies), in qcom_pcie_get_resources_2_3_2()
550 res->supplies); in qcom_pcie_get_resources_2_3_2()
554 res->clks[0].id = "aux"; in qcom_pcie_get_resources_2_3_2()
555 res->clks[1].id = "cfg"; in qcom_pcie_get_resources_2_3_2()
556 res->clks[2].id = "bus_master"; in qcom_pcie_get_resources_2_3_2()
557 res->clks[3].id = "bus_slave"; in qcom_pcie_get_resources_2_3_2()
559 ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks); in qcom_pcie_get_resources_2_3_2()
566 static void qcom_pcie_deinit_2_3_2(struct qcom_pcie *pcie) in qcom_pcie_deinit_2_3_2() argument
568 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2; in qcom_pcie_deinit_2_3_2()
570 clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); in qcom_pcie_deinit_2_3_2()
571 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); in qcom_pcie_deinit_2_3_2()
574 static int qcom_pcie_init_2_3_2(struct qcom_pcie *pcie) in qcom_pcie_init_2_3_2() argument
576 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2; in qcom_pcie_init_2_3_2()
577 struct dw_pcie *pci = pcie->pci; in qcom_pcie_init_2_3_2()
578 struct device *dev = pci->dev; in qcom_pcie_init_2_3_2()
581 ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies); in qcom_pcie_init_2_3_2()
587 ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); in qcom_pcie_init_2_3_2()
590 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); in qcom_pcie_init_2_3_2()
597 static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie) in qcom_pcie_post_init_2_3_2() argument
601 /* enable PCIe clocks and resets */ in qcom_pcie_post_init_2_3_2()
602 val = readl(pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_3_2()
604 writel(val, pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_3_2()
607 writel(0, pcie->parf + PARF_DBI_BASE_ADDR); in qcom_pcie_post_init_2_3_2()
610 val = readl(pcie->parf + PARF_SYS_CTRL); in qcom_pcie_post_init_2_3_2()
612 writel(val, pcie->parf + PARF_SYS_CTRL); in qcom_pcie_post_init_2_3_2()
614 val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); in qcom_pcie_post_init_2_3_2()
616 writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); in qcom_pcie_post_init_2_3_2()
618 val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); in qcom_pcie_post_init_2_3_2()
620 writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); in qcom_pcie_post_init_2_3_2()
622 qcom_pcie_clear_hpc(pcie->pci); in qcom_pcie_post_init_2_3_2()
627 static int qcom_pcie_get_resources_2_4_0(struct qcom_pcie *pcie) in qcom_pcie_get_resources_2_4_0() argument
629 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0; in qcom_pcie_get_resources_2_4_0()
630 struct dw_pcie *pci = pcie->pci; in qcom_pcie_get_resources_2_4_0()
631 struct device *dev = pci->dev; in qcom_pcie_get_resources_2_4_0()
632 bool is_ipq = of_device_is_compatible(dev->of_node, "qcom,pcie-ipq4019"); in qcom_pcie_get_resources_2_4_0()
635 res->clks[0].id = "aux"; in qcom_pcie_get_resources_2_4_0()
636 res->clks[1].id = "master_bus"; in qcom_pcie_get_resources_2_4_0()
637 res->clks[2].id = "slave_bus"; in qcom_pcie_get_resources_2_4_0()
638 res->clks[3].id = "iface"; in qcom_pcie_get_resources_2_4_0()
640 /* qcom,pcie-ipq4019 is defined without "iface" */ in qcom_pcie_get_resources_2_4_0()
641 res->num_clks = is_ipq ? 3 : 4; in qcom_pcie_get_resources_2_4_0()
643 ret = devm_clk_bulk_get(dev, res->num_clks, res->clks); in qcom_pcie_get_resources_2_4_0()
647 res->resets[0].id = "axi_m"; in qcom_pcie_get_resources_2_4_0()
648 res->resets[1].id = "axi_s"; in qcom_pcie_get_resources_2_4_0()
649 res->resets[2].id = "axi_m_sticky"; in qcom_pcie_get_resources_2_4_0()
650 res->resets[3].id = "pipe_sticky"; in qcom_pcie_get_resources_2_4_0()
651 res->resets[4].id = "pwr"; in qcom_pcie_get_resources_2_4_0()
652 res->resets[5].id = "ahb"; in qcom_pcie_get_resources_2_4_0()
653 res->resets[6].id = "pipe"; in qcom_pcie_get_resources_2_4_0()
654 res->resets[7].id = "axi_m_vmid"; in qcom_pcie_get_resources_2_4_0()
655 res->resets[8].id = "axi_s_xpu"; in qcom_pcie_get_resources_2_4_0()
656 res->resets[9].id = "parf"; in qcom_pcie_get_resources_2_4_0()
657 res->resets[10].id = "phy"; in qcom_pcie_get_resources_2_4_0()
658 res->resets[11].id = "phy_ahb"; in qcom_pcie_get_resources_2_4_0()
660 res->num_resets = is_ipq ? 12 : 6; in qcom_pcie_get_resources_2_4_0()
662 ret = devm_reset_control_bulk_get_exclusive(dev, res->num_resets, res->resets); in qcom_pcie_get_resources_2_4_0()
669 static void qcom_pcie_deinit_2_4_0(struct qcom_pcie *pcie) in qcom_pcie_deinit_2_4_0() argument
671 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0; in qcom_pcie_deinit_2_4_0()
673 reset_control_bulk_assert(res->num_resets, res->resets); in qcom_pcie_deinit_2_4_0()
674 clk_bulk_disable_unprepare(res->num_clks, res->clks); in qcom_pcie_deinit_2_4_0()
677 static int qcom_pcie_init_2_4_0(struct qcom_pcie *pcie) in qcom_pcie_init_2_4_0() argument
679 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0; in qcom_pcie_init_2_4_0()
680 struct dw_pcie *pci = pcie->pci; in qcom_pcie_init_2_4_0()
681 struct device *dev = pci->dev; in qcom_pcie_init_2_4_0()
684 ret = reset_control_bulk_assert(res->num_resets, res->resets); in qcom_pcie_init_2_4_0()
692 ret = reset_control_bulk_deassert(res->num_resets, res->resets); in qcom_pcie_init_2_4_0()
700 ret = clk_bulk_prepare_enable(res->num_clks, res->clks); in qcom_pcie_init_2_4_0()
702 reset_control_bulk_assert(res->num_resets, res->resets); in qcom_pcie_init_2_4_0()
709 static int qcom_pcie_get_resources_2_3_3(struct qcom_pcie *pcie) in qcom_pcie_get_resources_2_3_3() argument
711 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3; in qcom_pcie_get_resources_2_3_3()
712 struct dw_pcie *pci = pcie->pci; in qcom_pcie_get_resources_2_3_3()
713 struct device *dev = pci->dev; in qcom_pcie_get_resources_2_3_3()
716 res->clks[0].id = "iface"; in qcom_pcie_get_resources_2_3_3()
717 res->clks[1].id = "axi_m"; in qcom_pcie_get_resources_2_3_3()
718 res->clks[2].id = "axi_s"; in qcom_pcie_get_resources_2_3_3()
719 res->clks[3].id = "ahb"; in qcom_pcie_get_resources_2_3_3()
720 res->clks[4].id = "aux"; in qcom_pcie_get_resources_2_3_3()
722 ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks); in qcom_pcie_get_resources_2_3_3()
726 res->rst[0].id = "axi_m"; in qcom_pcie_get_resources_2_3_3()
727 res->rst[1].id = "axi_s"; in qcom_pcie_get_resources_2_3_3()
728 res->rst[2].id = "pipe"; in qcom_pcie_get_resources_2_3_3()
729 res->rst[3].id = "axi_m_sticky"; in qcom_pcie_get_resources_2_3_3()
730 res->rst[4].id = "sticky"; in qcom_pcie_get_resources_2_3_3()
731 res->rst[5].id = "ahb"; in qcom_pcie_get_resources_2_3_3()
732 res->rst[6].id = "sleep"; in qcom_pcie_get_resources_2_3_3()
734 ret = devm_reset_control_bulk_get_exclusive(dev, ARRAY_SIZE(res->rst), res->rst); in qcom_pcie_get_resources_2_3_3()
741 static void qcom_pcie_deinit_2_3_3(struct qcom_pcie *pcie) in qcom_pcie_deinit_2_3_3() argument
743 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3; in qcom_pcie_deinit_2_3_3()
745 clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); in qcom_pcie_deinit_2_3_3()
748 static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie) in qcom_pcie_init_2_3_3() argument
750 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3; in qcom_pcie_init_2_3_3()
751 struct dw_pcie *pci = pcie->pci; in qcom_pcie_init_2_3_3()
752 struct device *dev = pci->dev; in qcom_pcie_init_2_3_3()
755 ret = reset_control_bulk_assert(ARRAY_SIZE(res->rst), res->rst); in qcom_pcie_init_2_3_3()
763 ret = reset_control_bulk_deassert(ARRAY_SIZE(res->rst), res->rst); in qcom_pcie_init_2_3_3()
775 ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); in qcom_pcie_init_2_3_3()
788 reset_control_bulk_assert(ARRAY_SIZE(res->rst), res->rst); in qcom_pcie_init_2_3_3()
793 static int qcom_pcie_post_init_2_3_3(struct qcom_pcie *pcie) in qcom_pcie_post_init_2_3_3() argument
795 struct dw_pcie *pci = pcie->pci; in qcom_pcie_post_init_2_3_3()
799 writel(SLV_ADDR_SPACE_SZ, pcie->parf + PARF_SLV_ADDR_SPACE_SIZE); in qcom_pcie_post_init_2_3_3()
801 val = readl(pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_3_3()
803 writel(val, pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_3_3()
805 writel(0, pcie->parf + PARF_DBI_BASE_ADDR); in qcom_pcie_post_init_2_3_3()
810 pcie->parf + PARF_SYS_CTRL); in qcom_pcie_post_init_2_3_3()
811 writel(0, pcie->parf + PARF_Q2A_FLUSH); in qcom_pcie_post_init_2_3_3()
813 writel(PCI_COMMAND_MASTER, pci->dbi_base + PCI_COMMAND); in qcom_pcie_post_init_2_3_3()
817 writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP); in qcom_pcie_post_init_2_3_3()
819 val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP); in qcom_pcie_post_init_2_3_3()
821 writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP); in qcom_pcie_post_init_2_3_3()
823 writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset + in qcom_pcie_post_init_2_3_3()
831 static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) in qcom_pcie_get_resources_2_7_0() argument
833 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; in qcom_pcie_get_resources_2_7_0()
834 struct dw_pcie *pci = pcie->pci; in qcom_pcie_get_resources_2_7_0()
835 struct device *dev = pci->dev; in qcom_pcie_get_resources_2_7_0()
840 res->rst = devm_reset_control_array_get_exclusive(dev); in qcom_pcie_get_resources_2_7_0()
841 if (IS_ERR(res->rst)) in qcom_pcie_get_resources_2_7_0()
842 return PTR_ERR(res->rst); in qcom_pcie_get_resources_2_7_0()
844 res->supplies[0].supply = "vdda"; in qcom_pcie_get_resources_2_7_0()
845 res->supplies[1].supply = "vddpe-3v3"; in qcom_pcie_get_resources_2_7_0()
846 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies), in qcom_pcie_get_resources_2_7_0()
847 res->supplies); in qcom_pcie_get_resources_2_7_0()
852 res->clks[idx++].id = "aux"; in qcom_pcie_get_resources_2_7_0()
853 res->clks[idx++].id = "cfg"; in qcom_pcie_get_resources_2_7_0()
854 res->clks[idx++].id = "bus_master"; in qcom_pcie_get_resources_2_7_0()
855 res->clks[idx++].id = "bus_slave"; in qcom_pcie_get_resources_2_7_0()
856 res->clks[idx++].id = "slave_q2a"; in qcom_pcie_get_resources_2_7_0()
860 ret = devm_clk_bulk_get(dev, num_clks, res->clks); in qcom_pcie_get_resources_2_7_0()
864 res->clks[idx++].id = "tbu"; in qcom_pcie_get_resources_2_7_0()
865 res->clks[idx++].id = "ddrss_sf_tbu"; in qcom_pcie_get_resources_2_7_0()
866 res->clks[idx++].id = "aggre0"; in qcom_pcie_get_resources_2_7_0()
867 res->clks[idx++].id = "aggre1"; in qcom_pcie_get_resources_2_7_0()
868 res->clks[idx++].id = "noc_aggr"; in qcom_pcie_get_resources_2_7_0()
869 res->clks[idx++].id = "noc_aggr_4"; in qcom_pcie_get_resources_2_7_0()
870 res->clks[idx++].id = "noc_aggr_south_sf"; in qcom_pcie_get_resources_2_7_0()
871 res->clks[idx++].id = "cnoc_qx"; in qcom_pcie_get_resources_2_7_0()
872 res->clks[idx++].id = "sleep"; in qcom_pcie_get_resources_2_7_0()
873 res->clks[idx++].id = "cnoc_sf_axi"; in qcom_pcie_get_resources_2_7_0()
875 num_opt_clks = idx - num_clks; in qcom_pcie_get_resources_2_7_0()
876 res->num_clks = idx; in qcom_pcie_get_resources_2_7_0()
878 ret = devm_clk_bulk_get_optional(dev, num_opt_clks, res->clks + num_clks); in qcom_pcie_get_resources_2_7_0()
885 static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) in qcom_pcie_init_2_7_0() argument
887 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; in qcom_pcie_init_2_7_0()
888 struct dw_pcie *pci = pcie->pci; in qcom_pcie_init_2_7_0()
889 struct device *dev = pci->dev; in qcom_pcie_init_2_7_0()
893 ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies); in qcom_pcie_init_2_7_0()
899 ret = clk_bulk_prepare_enable(res->num_clks, res->clks); in qcom_pcie_init_2_7_0()
903 ret = reset_control_assert(res->rst); in qcom_pcie_init_2_7_0()
911 ret = reset_control_deassert(res->rst); in qcom_pcie_init_2_7_0()
920 /* configure PCIe to RC mode */ in qcom_pcie_init_2_7_0()
921 writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE); in qcom_pcie_init_2_7_0()
923 /* enable PCIe clocks and resets */ in qcom_pcie_init_2_7_0()
924 val = readl(pcie->parf + PARF_PHY_CTRL); in qcom_pcie_init_2_7_0()
926 writel(val, pcie->parf + PARF_PHY_CTRL); in qcom_pcie_init_2_7_0()
929 writel(0, pcie->parf + PARF_DBI_BASE_ADDR); in qcom_pcie_init_2_7_0()
932 val = readl(pcie->parf + PARF_SYS_CTRL); in qcom_pcie_init_2_7_0()
934 writel(val, pcie->parf + PARF_SYS_CTRL); in qcom_pcie_init_2_7_0()
936 val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); in qcom_pcie_init_2_7_0()
938 writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); in qcom_pcie_init_2_7_0()
941 val = readl(pcie->parf + PARF_PM_CTRL); in qcom_pcie_init_2_7_0()
943 writel(val, pcie->parf + PARF_PM_CTRL); in qcom_pcie_init_2_7_0()
945 val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); in qcom_pcie_init_2_7_0()
947 writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); in qcom_pcie_init_2_7_0()
951 clk_bulk_disable_unprepare(res->num_clks, res->clks); in qcom_pcie_init_2_7_0()
953 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); in qcom_pcie_init_2_7_0()
958 static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie) in qcom_pcie_post_init_2_7_0() argument
960 qcom_pcie_clear_hpc(pcie->pci); in qcom_pcie_post_init_2_7_0()
965 static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie) in qcom_pcie_deinit_2_7_0() argument
967 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; in qcom_pcie_deinit_2_7_0()
969 clk_bulk_disable_unprepare(res->num_clks, res->clks); in qcom_pcie_deinit_2_7_0()
971 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); in qcom_pcie_deinit_2_7_0()
974 static int qcom_pcie_config_sid_1_9_0(struct qcom_pcie *pcie) in qcom_pcie_config_sid_1_9_0() argument
983 void __iomem *bdf_to_sid_base = pcie->parf + PARF_BDF_TO_SID_TABLE_N; in qcom_pcie_config_sid_1_9_0()
984 struct device *dev = pcie->pci->dev; in qcom_pcie_config_sid_1_9_0()
989 of_get_property(dev->of_node, "iommu-map", &size); in qcom_pcie_config_sid_1_9_0()
995 return -ENOMEM; in qcom_pcie_config_sid_1_9_0()
997 of_property_read_u32_array(dev->of_node, "iommu-map", (u32 *)map, in qcom_pcie_config_sid_1_9_0()
1007 /* Extract the SMMU SID base from the first entry of iommu-map */ in qcom_pcie_config_sid_1_9_0()
1035 val = map[i].bdf << 16 | (map[i].smmu_sid - smmu_sid_base) << 8 | 0; in qcom_pcie_config_sid_1_9_0()
1044 static int qcom_pcie_get_resources_2_9_0(struct qcom_pcie *pcie) in qcom_pcie_get_resources_2_9_0() argument
1046 struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0; in qcom_pcie_get_resources_2_9_0()
1047 struct dw_pcie *pci = pcie->pci; in qcom_pcie_get_resources_2_9_0()
1048 struct device *dev = pci->dev; in qcom_pcie_get_resources_2_9_0()
1051 res->clks[0].id = "iface"; in qcom_pcie_get_resources_2_9_0()
1052 res->clks[1].id = "axi_m"; in qcom_pcie_get_resources_2_9_0()
1053 res->clks[2].id = "axi_s"; in qcom_pcie_get_resources_2_9_0()
1054 res->clks[3].id = "axi_bridge"; in qcom_pcie_get_resources_2_9_0()
1055 res->clks[4].id = "rchng"; in qcom_pcie_get_resources_2_9_0()
1057 ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks); in qcom_pcie_get_resources_2_9_0()
1061 res->rst = devm_reset_control_array_get_exclusive(dev); in qcom_pcie_get_resources_2_9_0()
1062 if (IS_ERR(res->rst)) in qcom_pcie_get_resources_2_9_0()
1063 return PTR_ERR(res->rst); in qcom_pcie_get_resources_2_9_0()
1068 static void qcom_pcie_deinit_2_9_0(struct qcom_pcie *pcie) in qcom_pcie_deinit_2_9_0() argument
1070 struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0; in qcom_pcie_deinit_2_9_0()
1072 clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); in qcom_pcie_deinit_2_9_0()
1075 static int qcom_pcie_init_2_9_0(struct qcom_pcie *pcie) in qcom_pcie_init_2_9_0() argument
1077 struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0; in qcom_pcie_init_2_9_0()
1078 struct device *dev = pcie->pci->dev; in qcom_pcie_init_2_9_0()
1081 ret = reset_control_assert(res->rst); in qcom_pcie_init_2_9_0()
1093 ret = reset_control_deassert(res->rst); in qcom_pcie_init_2_9_0()
1101 return clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); in qcom_pcie_init_2_9_0()
1104 static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie) in qcom_pcie_post_init_2_9_0() argument
1106 struct dw_pcie *pci = pcie->pci; in qcom_pcie_post_init_2_9_0()
1112 pcie->parf + PARF_SLV_ADDR_SPACE_SIZE); in qcom_pcie_post_init_2_9_0()
1114 val = readl(pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_9_0()
1116 writel(val, pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_9_0()
1118 writel(0, pcie->parf + PARF_DBI_BASE_ADDR); in qcom_pcie_post_init_2_9_0()
1120 writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE); in qcom_pcie_post_init_2_9_0()
1122 pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); in qcom_pcie_post_init_2_9_0()
1125 pci->dbi_base + GEN3_RELATED_OFF); in qcom_pcie_post_init_2_9_0()
1130 pcie->parf + PARF_SYS_CTRL); in qcom_pcie_post_init_2_9_0()
1132 writel(0, pcie->parf + PARF_Q2A_FLUSH); in qcom_pcie_post_init_2_9_0()
1136 writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP); in qcom_pcie_post_init_2_9_0()
1138 val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP); in qcom_pcie_post_init_2_9_0()
1140 writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP); in qcom_pcie_post_init_2_9_0()
1142 writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset + in qcom_pcie_post_init_2_9_0()
1148 writel(0, pcie->parf + PARF_BDF_TO_SID_TABLE_N + (4 * i)); in qcom_pcie_post_init_2_9_0()
1156 u16 val = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA); in qcom_pcie_link_up()
1164 struct qcom_pcie *pcie = to_qcom_pcie(pci); in qcom_pcie_host_init() local
1167 qcom_ep_reset_assert(pcie); in qcom_pcie_host_init()
1169 ret = pcie->cfg->ops->init(pcie); in qcom_pcie_host_init()
1173 ret = phy_set_mode_ext(pcie->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_RC); in qcom_pcie_host_init()
1177 ret = phy_power_on(pcie->phy); in qcom_pcie_host_init()
1181 if (pcie->cfg->ops->post_init) { in qcom_pcie_host_init()
1182 ret = pcie->cfg->ops->post_init(pcie); in qcom_pcie_host_init()
1187 qcom_ep_reset_deassert(pcie); in qcom_pcie_host_init()
1189 if (pcie->cfg->ops->config_sid) { in qcom_pcie_host_init()
1190 ret = pcie->cfg->ops->config_sid(pcie); in qcom_pcie_host_init()
1198 qcom_ep_reset_assert(pcie); in qcom_pcie_host_init()
1200 phy_power_off(pcie->phy); in qcom_pcie_host_init()
1202 pcie->cfg->ops->deinit(pcie); in qcom_pcie_host_init()
1210 struct qcom_pcie *pcie = to_qcom_pcie(pci); in qcom_pcie_host_deinit() local
1212 qcom_ep_reset_assert(pcie); in qcom_pcie_host_deinit()
1213 phy_power_off(pcie->phy); in qcom_pcie_host_deinit()
1214 pcie->cfg->ops->deinit(pcie); in qcom_pcie_host_deinit()
1332 static int qcom_pcie_icc_init(struct qcom_pcie *pcie) in qcom_pcie_icc_init() argument
1334 struct dw_pcie *pci = pcie->pci; in qcom_pcie_icc_init()
1337 pcie->icc_mem = devm_of_icc_get(pci->dev, "pcie-mem"); in qcom_pcie_icc_init()
1338 if (IS_ERR(pcie->icc_mem)) in qcom_pcie_icc_init()
1339 return PTR_ERR(pcie->icc_mem); in qcom_pcie_icc_init()
1345 * Set an initial peak bandwidth corresponding to single-lane Gen 1 in qcom_pcie_icc_init()
1346 * for the pcie-mem path. in qcom_pcie_icc_init()
1348 ret = icc_set_bw(pcie->icc_mem, 0, MBps_to_icc(250)); in qcom_pcie_icc_init()
1350 dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n", in qcom_pcie_icc_init()
1358 static void qcom_pcie_icc_update(struct qcom_pcie *pcie) in qcom_pcie_icc_update() argument
1360 struct dw_pcie *pci = pcie->pci; in qcom_pcie_icc_update()
1365 if (!pcie->icc_mem) in qcom_pcie_icc_update()
1369 status = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA); in qcom_pcie_icc_update()
1393 ret = icc_set_bw(pcie->icc_mem, 0, width * bw); in qcom_pcie_icc_update()
1395 dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n", in qcom_pcie_icc_update()
1402 struct qcom_pcie *pcie = (struct qcom_pcie *)dev_get_drvdata(s->private); in qcom_pcie_link_transition_count() local
1405 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_PM_LINKST_IN_L0S)); in qcom_pcie_link_transition_count()
1408 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_PM_LINKST_IN_L1)); in qcom_pcie_link_transition_count()
1411 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1)); in qcom_pcie_link_transition_count()
1414 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2)); in qcom_pcie_link_transition_count()
1417 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_PM_LINKST_IN_L2)); in qcom_pcie_link_transition_count()
1422 static void qcom_pcie_init_debugfs(struct qcom_pcie *pcie) in qcom_pcie_init_debugfs() argument
1424 struct dw_pcie *pci = pcie->pci; in qcom_pcie_init_debugfs()
1425 struct device *dev = pci->dev; in qcom_pcie_init_debugfs()
1428 name = devm_kasprintf(dev, GFP_KERNEL, "%pOFP", dev->of_node); in qcom_pcie_init_debugfs()
1432 pcie->debugfs = debugfs_create_dir(name, NULL); in qcom_pcie_init_debugfs()
1433 debugfs_create_devm_seqfile(dev, "link_transition_count", pcie->debugfs, in qcom_pcie_init_debugfs()
1440 struct device *dev = &pdev->dev; in qcom_pcie_probe()
1441 struct qcom_pcie *pcie; in qcom_pcie_probe() local
1448 if (!pcie_cfg || !pcie_cfg->ops) { in qcom_pcie_probe()
1450 return -EINVAL; in qcom_pcie_probe()
1453 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); in qcom_pcie_probe()
1454 if (!pcie) in qcom_pcie_probe()
1455 return -ENOMEM; in qcom_pcie_probe()
1459 return -ENOMEM; in qcom_pcie_probe()
1466 pci->dev = dev; in qcom_pcie_probe()
1467 pci->ops = &dw_pcie_ops; in qcom_pcie_probe()
1468 pp = &pci->pp; in qcom_pcie_probe()
1470 pcie->pci = pci; in qcom_pcie_probe()
1472 pcie->cfg = pcie_cfg; in qcom_pcie_probe()
1474 pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_HIGH); in qcom_pcie_probe()
1475 if (IS_ERR(pcie->reset)) { in qcom_pcie_probe()
1476 ret = PTR_ERR(pcie->reset); in qcom_pcie_probe()
1480 pcie->parf = devm_platform_ioremap_resource_byname(pdev, "parf"); in qcom_pcie_probe()
1481 if (IS_ERR(pcie->parf)) { in qcom_pcie_probe()
1482 ret = PTR_ERR(pcie->parf); in qcom_pcie_probe()
1486 pcie->elbi = devm_platform_ioremap_resource_byname(pdev, "elbi"); in qcom_pcie_probe()
1487 if (IS_ERR(pcie->elbi)) { in qcom_pcie_probe()
1488 ret = PTR_ERR(pcie->elbi); in qcom_pcie_probe()
1495 pcie->mhi = devm_ioremap_resource(dev, res); in qcom_pcie_probe()
1496 if (IS_ERR(pcie->mhi)) { in qcom_pcie_probe()
1497 ret = PTR_ERR(pcie->mhi); in qcom_pcie_probe()
1502 pcie->phy = devm_phy_optional_get(dev, "pciephy"); in qcom_pcie_probe()
1503 if (IS_ERR(pcie->phy)) { in qcom_pcie_probe()
1504 ret = PTR_ERR(pcie->phy); in qcom_pcie_probe()
1508 ret = qcom_pcie_icc_init(pcie); in qcom_pcie_probe()
1512 ret = pcie->cfg->ops->get_resources(pcie); in qcom_pcie_probe()
1516 pp->ops = &qcom_pcie_dw_ops; in qcom_pcie_probe()
1518 ret = phy_init(pcie->phy); in qcom_pcie_probe()
1522 platform_set_drvdata(pdev, pcie); in qcom_pcie_probe()
1530 qcom_pcie_icc_update(pcie); in qcom_pcie_probe()
1532 if (pcie->mhi) in qcom_pcie_probe()
1533 qcom_pcie_init_debugfs(pcie); in qcom_pcie_probe()
1538 phy_exit(pcie->phy); in qcom_pcie_probe()
1548 struct qcom_pcie *pcie = dev_get_drvdata(dev); in qcom_pcie_suspend_noirq() local
1555 ret = icc_set_bw(pcie->icc_mem, 0, kBps_to_icc(1)); in qcom_pcie_suspend_noirq()
1562 * Turn OFF the resources only for controllers without active PCIe in qcom_pcie_suspend_noirq()
1566 * Turning OFF the resources for controllers with active PCIe devices in qcom_pcie_suspend_noirq()
1568 * as kernel tries to access the PCIe devices config space for masking in qcom_pcie_suspend_noirq()
1576 if (!dw_pcie_link_up(pcie->pci)) { in qcom_pcie_suspend_noirq()
1577 qcom_pcie_host_deinit(&pcie->pci->pp); in qcom_pcie_suspend_noirq()
1578 pcie->suspended = true; in qcom_pcie_suspend_noirq()
1586 struct qcom_pcie *pcie = dev_get_drvdata(dev); in qcom_pcie_resume_noirq() local
1589 if (pcie->suspended) { in qcom_pcie_resume_noirq()
1590 ret = qcom_pcie_host_init(&pcie->pci->pp); in qcom_pcie_resume_noirq()
1594 pcie->suspended = false; in qcom_pcie_resume_noirq()
1597 qcom_pcie_icc_update(pcie); in qcom_pcie_resume_noirq()
1603 { .compatible = "qcom,pcie-apq8064", .data = &cfg_2_1_0 },
1604 { .compatible = "qcom,pcie-apq8084", .data = &cfg_1_0_0 },
1605 { .compatible = "qcom,pcie-ipq4019", .data = &cfg_2_4_0 },
1606 { .compatible = "qcom,pcie-ipq6018", .data = &cfg_2_9_0 },
1607 { .compatible = "qcom,pcie-ipq8064", .data = &cfg_2_1_0 },
1608 { .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 },
1609 { .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 },
1610 { .compatible = "qcom,pcie-ipq8074-gen3", .data = &cfg_2_9_0 },
1611 { .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 },
1612 { .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 },
1613 { .compatible = "qcom,pcie-sa8540p", .data = &cfg_1_9_0 },
1614 { .compatible = "qcom,pcie-sa8775p", .data = &cfg_1_9_0},
1615 { .compatible = "qcom,pcie-sc7280", .data = &cfg_1_9_0 },
1616 { .compatible = "qcom,pcie-sc8180x", .data = &cfg_1_9_0 },
1617 { .compatible = "qcom,pcie-sc8280xp", .data = &cfg_1_9_0 },
1618 { .compatible = "qcom,pcie-sdm845", .data = &cfg_2_7_0 },
1619 { .compatible = "qcom,pcie-sdx55", .data = &cfg_1_9_0 },
1620 { .compatible = "qcom,pcie-sm8150", .data = &cfg_1_9_0 },
1621 { .compatible = "qcom,pcie-sm8250", .data = &cfg_1_9_0 },
1622 { .compatible = "qcom,pcie-sm8350", .data = &cfg_1_9_0 },
1623 { .compatible = "qcom,pcie-sm8450-pcie0", .data = &cfg_1_9_0 },
1624 { .compatible = "qcom,pcie-sm8450-pcie1", .data = &cfg_1_9_0 },
1625 { .compatible = "qcom,pcie-sm8550", .data = &cfg_1_9_0 },
1631 dev->class = PCI_CLASS_BRIDGE_PCI_NORMAL; in qcom_fixup_class()
1648 .name = "qcom-pcie",