103 	u16 isr;  member
155 	unsigned int isr = readl_relaxed(rtc->base + regs->isr);  in stm32_rtc_enter_init_mode()  local
157 	if (!(isr & STM32_RTC_ISR_INITF)) {  in stm32_rtc_enter_init_mode()
158 		isr |= STM32_RTC_ISR_INIT;  in stm32_rtc_enter_init_mode()
159 		writel_relaxed(isr, rtc->base + regs->isr);  in stm32_rtc_enter_init_mode()
167 		return readl_relaxed_poll_timeout_atomic(rtc->base + regs->isr, isr,  in stm32_rtc_enter_init_mode()
168 							 (isr & STM32_RTC_ISR_INITF),  in stm32_rtc_enter_init_mode()
178 	unsigned int isr = readl_relaxed(rtc->base + regs->isr);  in stm32_rtc_exit_init_mode()  local
180 	isr &= ~STM32_RTC_ISR_INIT;  in stm32_rtc_exit_init_mode()
181 	writel_relaxed(isr, rtc->base + regs->isr);  in stm32_rtc_exit_init_mode()
187 	unsigned int isr = readl_relaxed(rtc->base + regs->isr);  in stm32_rtc_wait_sync()  local
189 	isr &= ~STM32_RTC_ISR_RSF;  in stm32_rtc_wait_sync()
190 	writel_relaxed(isr, rtc->base + regs->isr);  in stm32_rtc_wait_sync()
196 	return readl_relaxed_poll_timeout_atomic(rtc->base + regs->isr,  in stm32_rtc_wait_sync()
197 						 isr,  in stm32_rtc_wait_sync()
198 						 (isr & STM32_RTC_ISR_RSF),  in stm32_rtc_wait_sync()
476 	unsigned int cr, isr, alrmar;  in stm32_rtc_set_alarm()  local
514 	ret = readl_relaxed_poll_timeout_atomic(rtc->base + regs->isr,  in stm32_rtc_set_alarm()
515 						isr,  in stm32_rtc_set_alarm()
516 						(isr & STM32_RTC_ISR_ALRAWF),  in stm32_rtc_set_alarm()
548 	writel_relaxed(readl_relaxed(rtc->base + regs->isr) & ~flags,  in stm32_rtc_clear_events()
549 		       rtc->base + regs->isr);  in stm32_rtc_clear_events()
560 		.isr = 0x0C,
564 		.sr = 0x0C, /* set to ISR offset to ease alarm management */
582 		.isr = 0x0C,
586 		.sr = 0x0C, /* set to ISR offset to ease alarm management */
613 		.isr = 0x0C, /* named RTC_ICSR on stm32mp1 */
841 	if (!(readl_relaxed(rtc->base + regs->isr) & STM32_RTC_ISR_INITS))  in stm32_rtc_probe()