Lines Matching +full:stm32h7 +full:- +full:uart
1 // SPDX-License-Identifier: GPL-2.0
9 * Inspired by st-asc.c from STMicroelectronics (c)
15 #include <linux/dma-direction.h>
17 #include <linux/dma-mapping.h>
36 #include "stm32-usart.h"
120 val = readl_relaxed(port->membase + reg); in stm32_usart_set_bits()
122 writel_relaxed(val, port->membase + reg); in stm32_usart_set_bits()
129 val = readl_relaxed(port->membase + reg); in stm32_usart_clr_bits()
131 writel_relaxed(val, port->membase + reg); in stm32_usart_clr_bits()
137 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_tx_empty()
139 if (readl_relaxed(port->membase + ofs->isr) & USART_SR_TC) in stm32_usart_tx_empty()
148 struct serial_rs485 *rs485conf = &port->rs485; in stm32_usart_rs485_rts_enable()
150 if (stm32_port->hw_flow_control || in stm32_usart_rs485_rts_enable()
151 !(rs485conf->flags & SER_RS485_ENABLED)) in stm32_usart_rs485_rts_enable()
154 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { in stm32_usart_rs485_rts_enable()
155 mctrl_gpio_set(stm32_port->gpios, in stm32_usart_rs485_rts_enable()
156 stm32_port->port.mctrl | TIOCM_RTS); in stm32_usart_rs485_rts_enable()
158 mctrl_gpio_set(stm32_port->gpios, in stm32_usart_rs485_rts_enable()
159 stm32_port->port.mctrl & ~TIOCM_RTS); in stm32_usart_rs485_rts_enable()
166 struct serial_rs485 *rs485conf = &port->rs485; in stm32_usart_rs485_rts_disable()
168 if (stm32_port->hw_flow_control || in stm32_usart_rs485_rts_disable()
169 !(rs485conf->flags & SER_RS485_ENABLED)) in stm32_usart_rs485_rts_disable()
172 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { in stm32_usart_rs485_rts_disable()
173 mctrl_gpio_set(stm32_port->gpios, in stm32_usart_rs485_rts_disable()
174 stm32_port->port.mctrl & ~TIOCM_RTS); in stm32_usart_rs485_rts_disable()
176 mctrl_gpio_set(stm32_port->gpios, in stm32_usart_rs485_rts_disable()
177 stm32_port->port.mctrl | TIOCM_RTS); in stm32_usart_rs485_rts_disable()
222 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_config_rs485()
223 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; in stm32_usart_config_rs485()
227 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); in stm32_usart_config_rs485()
229 if (rs485conf->flags & SER_RS485_ENABLED) { in stm32_usart_config_rs485()
230 cr1 = readl_relaxed(port->membase + ofs->cr1); in stm32_usart_config_rs485()
231 cr3 = readl_relaxed(port->membase + ofs->cr3); in stm32_usart_config_rs485()
232 usartdiv = readl_relaxed(port->membase + ofs->brr); in stm32_usart_config_rs485()
240 baud = DIV_ROUND_CLOSEST(port->uartclk, usartdiv); in stm32_usart_config_rs485()
242 rs485conf->delay_rts_before_send, in stm32_usart_config_rs485()
243 rs485conf->delay_rts_after_send, in stm32_usart_config_rs485()
246 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) in stm32_usart_config_rs485()
251 writel_relaxed(cr3, port->membase + ofs->cr3); in stm32_usart_config_rs485()
252 writel_relaxed(cr1, port->membase + ofs->cr1); in stm32_usart_config_rs485()
254 if (!port->rs485_rx_during_tx_gpio) in stm32_usart_config_rs485()
255 rs485conf->flags |= SER_RS485_RX_DURING_TX; in stm32_usart_config_rs485()
258 stm32_usart_clr_bits(port, ofs->cr3, in stm32_usart_config_rs485()
260 stm32_usart_clr_bits(port, ofs->cr1, in stm32_usart_config_rs485()
264 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); in stm32_usart_config_rs485()
278 struct serial_rs485 *rs485conf = &port->rs485; in stm32_usart_init_rs485()
280 rs485conf->flags = 0; in stm32_usart_init_rs485()
281 rs485conf->delay_rts_before_send = 0; in stm32_usart_init_rs485()
282 rs485conf->delay_rts_after_send = 0; in stm32_usart_init_rs485()
284 if (!pdev->dev.of_node) in stm32_usart_init_rs485()
285 return -ENODEV; in stm32_usart_init_rs485()
292 return stm32_port->rx_ch ? stm32_port->rx_dma_busy : false; in stm32_usart_rx_dma_started()
297 dmaengine_terminate_async(stm32_port->rx_ch); in stm32_usart_rx_dma_terminate()
298 stm32_port->rx_dma_busy = false; in stm32_usart_rx_dma_terminate()
308 struct uart_port *port = &stm32_port->port; in stm32_usart_dma_pause_resume()
313 return -EPERM; in stm32_usart_dma_pause_resume()
315 dma_status = dmaengine_tx_status(chan, chan->cookie, NULL); in stm32_usart_dma_pause_resume()
317 return -EAGAIN; in stm32_usart_dma_pause_resume()
321 dev_err(port->dev, "DMA failed with error code: %d\n", ret); in stm32_usart_dma_pause_resume()
329 return stm32_usart_dma_pause_resume(stm32_port, stm32_port->rx_ch, in stm32_usart_rx_dma_pause()
337 return stm32_usart_dma_pause_resume(stm32_port, stm32_port->rx_ch, in stm32_usart_rx_dma_resume()
347 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_pending_rx_pio()
349 *sr = readl_relaxed(port->membase + ofs->isr); in stm32_usart_pending_rx_pio()
367 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_get_char_pio()
370 c = readl_relaxed(port->membase + ofs->rdr); in stm32_usart_get_char_pio()
372 c &= stm32_port->rdr_mask; in stm32_usart_get_char_pio()
380 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_receive_chars_pio()
396 * Clear errors flags for stm32f7 and stm32h7 compatible in stm32_usart_receive_chars_pio()
398 * cleared by the sequence [read SR - read DR]. in stm32_usart_receive_chars_pio()
400 if ((sr & USART_SR_ERR_MASK) && ofs->icr != UNDEF_REG) in stm32_usart_receive_chars_pio()
402 port->membase + ofs->icr); in stm32_usart_receive_chars_pio()
405 port->icount.rx++; in stm32_usart_receive_chars_pio()
409 port->icount.overrun++; in stm32_usart_receive_chars_pio()
411 port->icount.parity++; in stm32_usart_receive_chars_pio()
415 port->icount.brk++; in stm32_usart_receive_chars_pio()
419 port->icount.frame++; in stm32_usart_receive_chars_pio()
423 sr &= port->read_status_mask; in stm32_usart_receive_chars_pio()
446 struct tty_port *ttyport = &stm32_port->port.state->port; in stm32_usart_push_buffer_dma()
450 dma_start = stm32_port->rx_buf + (RX_BUF_L - stm32_port->last_res); in stm32_usart_push_buffer_dma()
457 if (!(stm32_port->rdr_mask == (BIT(8) - 1))) in stm32_usart_push_buffer_dma()
459 *(dma_start + i) &= stm32_port->rdr_mask; in stm32_usart_push_buffer_dma()
462 port->icount.rx += dma_count; in stm32_usart_push_buffer_dma()
464 port->icount.buf_overrun++; in stm32_usart_push_buffer_dma()
465 stm32_port->last_res -= dma_count; in stm32_usart_push_buffer_dma()
466 if (stm32_port->last_res == 0) in stm32_usart_push_buffer_dma()
467 stm32_port->last_res = RX_BUF_L; in stm32_usart_push_buffer_dma()
476 if (stm32_port->rx_dma_state.residue > stm32_port->last_res) { in stm32_usart_receive_chars_dma()
478 dma_size = stm32_port->last_res; in stm32_usart_receive_chars_dma()
483 dma_size = stm32_port->last_res - stm32_port->rx_dma_state.residue; in stm32_usart_receive_chars_dma()
493 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_receive_chars()
499 rx_dma_status = dmaengine_tx_status(stm32_port->rx_ch, in stm32_usart_receive_chars()
500 stm32_port->rx_ch->cookie, in stm32_usart_receive_chars()
501 &stm32_port->rx_dma_state); in stm32_usart_receive_chars()
506 sr = readl_relaxed(port->membase + ofs->isr); in stm32_usart_receive_chars()
509 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR); in stm32_usart_receive_chars()
515 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAR); in stm32_usart_receive_chars()
521 dev_dbg(port->dev, "DMA error, fallback to irq mode\n"); in stm32_usart_receive_chars()
534 struct tty_port *tport = &port->state->port; in stm32_usart_rx_dma_complete()
538 spin_lock_irqsave(&port->lock, flags); in stm32_usart_rx_dma_complete()
552 if (stm32_port->throttled) in stm32_usart_rx_dma_start_or_resume()
555 if (stm32_port->rx_dma_busy) { in stm32_usart_rx_dma_start_or_resume()
556 rx_dma_status = dmaengine_tx_status(stm32_port->rx_ch, in stm32_usart_rx_dma_start_or_resume()
557 stm32_port->rx_ch->cookie, in stm32_usart_rx_dma_start_or_resume()
565 dev_err(port->dev, "DMA failed : status error.\n"); in stm32_usart_rx_dma_start_or_resume()
569 stm32_port->rx_dma_busy = true; in stm32_usart_rx_dma_start_or_resume()
571 stm32_port->last_res = RX_BUF_L; in stm32_usart_rx_dma_start_or_resume()
573 desc = dmaengine_prep_dma_cyclic(stm32_port->rx_ch, in stm32_usart_rx_dma_start_or_resume()
574 stm32_port->rx_dma_buf, in stm32_usart_rx_dma_start_or_resume()
579 dev_err(port->dev, "rx dma prep cyclic failed\n"); in stm32_usart_rx_dma_start_or_resume()
580 stm32_port->rx_dma_busy = false; in stm32_usart_rx_dma_start_or_resume()
581 return -ENODEV; in stm32_usart_rx_dma_start_or_resume()
584 desc->callback = stm32_usart_rx_dma_complete; in stm32_usart_rx_dma_start_or_resume()
585 desc->callback_param = port; in stm32_usart_rx_dma_start_or_resume()
590 dmaengine_terminate_sync(stm32_port->rx_ch); in stm32_usart_rx_dma_start_or_resume()
591 stm32_port->rx_dma_busy = false; in stm32_usart_rx_dma_start_or_resume()
596 dma_async_issue_pending(stm32_port->rx_ch); in stm32_usart_rx_dma_start_or_resume()
603 dmaengine_terminate_async(stm32_port->tx_ch); in stm32_usart_tx_dma_terminate()
604 stm32_port->tx_dma_busy = false; in stm32_usart_tx_dma_terminate()
616 return stm32_port->tx_dma_busy; in stm32_usart_tx_dma_started()
621 return stm32_usart_dma_pause_resume(stm32_port, stm32_port->tx_ch, in stm32_usart_tx_dma_pause()
629 return stm32_usart_dma_pause_resume(stm32_port, stm32_port->tx_ch, in stm32_usart_tx_dma_resume()
644 spin_lock_irqsave(&port->lock, flags); in stm32_usart_tx_dma_complete()
646 spin_unlock_irqrestore(&port->lock, flags); in stm32_usart_tx_dma_complete()
652 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_tx_interrupt_enable()
658 if (stm32_port->fifoen && stm32_port->txftcfg >= 0) in stm32_usart_tx_interrupt_enable()
659 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_TXFTIE); in stm32_usart_tx_interrupt_enable()
661 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_TXEIE); in stm32_usart_tx_interrupt_enable()
667 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_tc_interrupt_enable()
669 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_TCIE); in stm32_usart_tc_interrupt_enable()
675 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_tx_interrupt_disable()
677 if (stm32_port->fifoen && stm32_port->txftcfg >= 0) in stm32_usart_tx_interrupt_disable()
678 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_TXFTIE); in stm32_usart_tx_interrupt_disable()
680 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_TXEIE); in stm32_usart_tx_interrupt_disable()
686 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_tc_interrupt_disable()
688 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_TCIE); in stm32_usart_tc_interrupt_disable()
694 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_transmit_chars_pio()
695 struct circ_buf *xmit = &port->state->xmit; in stm32_usart_transmit_chars_pio()
699 if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE)) in stm32_usart_transmit_chars_pio()
701 writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr); in stm32_usart_transmit_chars_pio()
715 struct circ_buf *xmit = &port->state->xmit; in stm32_usart_transmit_chars_dma()
722 if (ret < 0 && ret != -EAGAIN) in stm32_usart_transmit_chars_dma()
732 if (xmit->tail < xmit->head) { in stm32_usart_transmit_chars_dma()
733 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], count); in stm32_usart_transmit_chars_dma()
735 size_t one = UART_XMIT_SIZE - xmit->tail; in stm32_usart_transmit_chars_dma()
740 two = count - one; in stm32_usart_transmit_chars_dma()
742 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], one); in stm32_usart_transmit_chars_dma()
744 memcpy(&stm32port->tx_buf[one], &xmit->buf[0], two); in stm32_usart_transmit_chars_dma()
747 desc = dmaengine_prep_slave_single(stm32port->tx_ch, in stm32_usart_transmit_chars_dma()
748 stm32port->tx_dma_buf, in stm32_usart_transmit_chars_dma()
762 stm32port->tx_dma_busy = true; in stm32_usart_transmit_chars_dma()
764 desc->callback = stm32_usart_tx_dma_complete; in stm32_usart_transmit_chars_dma()
765 desc->callback_param = port; in stm32_usart_transmit_chars_dma()
771 dev_err(port->dev, "DMA failed with error code: %d\n", ret); in stm32_usart_transmit_chars_dma()
777 dma_async_issue_pending(stm32port->tx_ch); in stm32_usart_transmit_chars_dma()
790 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_transmit_chars()
791 struct circ_buf *xmit = &port->state->xmit; in stm32_usart_transmit_chars()
795 if (!stm32_port->hw_flow_control && in stm32_usart_transmit_chars()
796 port->rs485.flags & SER_RS485_ENABLED && in stm32_usart_transmit_chars()
797 (port->x_char || in stm32_usart_transmit_chars()
803 if (port->x_char) { in stm32_usart_transmit_chars()
809 readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr, in stm32_usart_transmit_chars()
814 dev_warn(port->dev, "1 character may be erased\n"); in stm32_usart_transmit_chars()
816 writel_relaxed(port->x_char, port->membase + ofs->tdr); in stm32_usart_transmit_chars()
817 port->x_char = 0; in stm32_usart_transmit_chars()
818 port->icount.tx++; in stm32_usart_transmit_chars()
830 if (ofs->icr == UNDEF_REG) in stm32_usart_transmit_chars()
831 stm32_usart_clr_bits(port, ofs->isr, USART_SR_TC); in stm32_usart_transmit_chars()
833 writel_relaxed(USART_ICR_TCCF, port->membase + ofs->icr); in stm32_usart_transmit_chars()
835 if (stm32_port->tx_ch) in stm32_usart_transmit_chars()
845 if (!stm32_port->hw_flow_control && in stm32_usart_transmit_chars()
846 port->rs485.flags & SER_RS485_ENABLED) { in stm32_usart_transmit_chars()
855 struct tty_port *tport = &port->state->port; in stm32_usart_interrupt()
857 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_interrupt()
861 sr = readl_relaxed(port->membase + ofs->isr); in stm32_usart_interrupt()
863 if (!stm32_port->hw_flow_control && in stm32_usart_interrupt()
864 port->rs485.flags & SER_RS485_ENABLED && in stm32_usart_interrupt()
870 if ((sr & USART_SR_RTOF) && ofs->icr != UNDEF_REG) in stm32_usart_interrupt()
872 port->membase + ofs->icr); in stm32_usart_interrupt()
874 if ((sr & USART_SR_WUF) && ofs->icr != UNDEF_REG) { in stm32_usart_interrupt()
877 port->membase + ofs->icr); in stm32_usart_interrupt()
878 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_WUFIE); in stm32_usart_interrupt()
879 if (irqd_is_wakeup_set(irq_get_irq_data(port->irq))) in stm32_usart_interrupt()
880 pm_wakeup_event(tport->tty->dev, 0); in stm32_usart_interrupt()
887 if (!stm32_port->throttled) { in stm32_usart_interrupt()
890 spin_lock(&port->lock); in stm32_usart_interrupt()
898 if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch)) { in stm32_usart_interrupt()
899 spin_lock(&port->lock); in stm32_usart_interrupt()
901 spin_unlock(&port->lock); in stm32_usart_interrupt()
905 if (stm32_usart_rx_dma_started(stm32_port) && !stm32_port->throttled) { in stm32_usart_interrupt()
906 spin_lock(&port->lock); in stm32_usart_interrupt()
919 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_set_mctrl()
921 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) in stm32_usart_set_mctrl()
922 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_RTSE); in stm32_usart_set_mctrl()
924 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_RTSE); in stm32_usart_set_mctrl()
926 mctrl_gpio_set(stm32_port->gpios, mctrl); in stm32_usart_set_mctrl()
937 return mctrl_gpio_get(stm32_port->gpios, &ret); in stm32_usart_get_mctrl()
942 mctrl_gpio_enable_ms(to_stm32_port(port)->gpios); in stm32_usart_enable_ms()
947 mctrl_gpio_disable_ms(to_stm32_port(port)->gpios); in stm32_usart_disable_ms()
966 struct circ_buf *xmit = &port->state->xmit; in stm32_usart_start_tx()
968 if (uart_circ_empty(xmit) && !port->x_char) { in stm32_usart_start_tx()
983 if (stm32_port->tx_ch) in stm32_usart_flush_buffer()
991 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_throttle()
994 spin_lock_irqsave(&port->lock, flags); in stm32_usart_throttle()
1002 stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq); in stm32_usart_throttle()
1003 if (stm32_port->cr3_irq) in stm32_usart_throttle()
1004 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq); in stm32_usart_throttle()
1006 stm32_port->throttled = true; in stm32_usart_throttle()
1007 spin_unlock_irqrestore(&port->lock, flags); in stm32_usart_throttle()
1014 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_unthrottle()
1017 spin_lock_irqsave(&port->lock, flags); in stm32_usart_unthrottle()
1018 stm32_usart_set_bits(port, ofs->cr1, stm32_port->cr1_irq); in stm32_usart_unthrottle()
1019 if (stm32_port->cr3_irq) in stm32_usart_unthrottle()
1020 stm32_usart_set_bits(port, ofs->cr3, stm32_port->cr3_irq); in stm32_usart_unthrottle()
1022 stm32_port->throttled = false; in stm32_usart_unthrottle()
1028 if (stm32_port->rx_ch) in stm32_usart_unthrottle()
1031 spin_unlock_irqrestore(&port->lock, flags); in stm32_usart_unthrottle()
1038 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_stop_rx()
1043 stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq); in stm32_usart_stop_rx()
1044 if (stm32_port->cr3_irq) in stm32_usart_stop_rx()
1045 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq); in stm32_usart_stop_rx()
1048 /* Handle breaks - ignored by us */
1056 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_startup()
1057 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; in stm32_usart_startup()
1058 const char *name = to_platform_device(port->dev)->name; in stm32_usart_startup()
1062 ret = request_irq(port->irq, stm32_usart_interrupt, in stm32_usart_startup()
1067 if (stm32_port->swap) { in stm32_usart_startup()
1068 val = readl_relaxed(port->membase + ofs->cr2); in stm32_usart_startup()
1070 writel_relaxed(val, port->membase + ofs->cr2); in stm32_usart_startup()
1074 if (ofs->rqr != UNDEF_REG) in stm32_usart_startup()
1075 writel_relaxed(USART_RQR_RXFRQ, port->membase + ofs->rqr); in stm32_usart_startup()
1077 if (stm32_port->rx_ch) { in stm32_usart_startup()
1080 free_irq(port->irq, port); in stm32_usart_startup()
1086 val = stm32_port->cr1_irq | USART_CR1_RE | BIT(cfg->uart_enable_bit); in stm32_usart_startup()
1087 stm32_usart_set_bits(port, ofs->cr1, val); in stm32_usart_startup()
1095 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_shutdown()
1096 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; in stm32_usart_shutdown()
1103 if (stm32_port->tx_ch) in stm32_usart_shutdown()
1104 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); in stm32_usart_shutdown()
1110 val |= stm32_port->cr1_irq | USART_CR1_RE; in stm32_usart_shutdown()
1111 val |= BIT(cfg->uart_enable_bit); in stm32_usart_shutdown()
1112 if (stm32_port->fifoen) in stm32_usart_shutdown()
1115 ret = readl_relaxed_poll_timeout(port->membase + ofs->isr, in stm32_usart_shutdown()
1121 dev_err(port->dev, "Transmission is not complete\n"); in stm32_usart_shutdown()
1124 if (stm32_port->rx_ch) { in stm32_usart_shutdown()
1126 dmaengine_synchronize(stm32_port->rx_ch); in stm32_usart_shutdown()
1130 if (ofs->rqr != UNDEF_REG) in stm32_usart_shutdown()
1132 port->membase + ofs->rqr); in stm32_usart_shutdown()
1134 stm32_usart_clr_bits(port, ofs->cr1, val); in stm32_usart_shutdown()
1136 free_irq(port->irq, port); in stm32_usart_shutdown()
1144 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_set_termios()
1145 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; in stm32_usart_set_termios()
1146 struct serial_rs485 *rs485conf = &port->rs485; in stm32_usart_set_termios()
1149 tcflag_t cflag = termios->c_cflag; in stm32_usart_set_termios()
1154 if (!stm32_port->hw_flow_control) in stm32_usart_set_termios()
1157 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8); in stm32_usart_set_termios()
1159 spin_lock_irqsave(&port->lock, flags); in stm32_usart_set_termios()
1161 ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr, in stm32_usart_set_termios()
1168 dev_err(port->dev, "Transmission is not complete\n"); in stm32_usart_set_termios()
1171 writel_relaxed(0, port->membase + ofs->cr1); in stm32_usart_set_termios()
1174 if (ofs->rqr != UNDEF_REG) in stm32_usart_set_termios()
1176 port->membase + ofs->rqr); in stm32_usart_set_termios()
1179 if (stm32_port->fifoen) in stm32_usart_set_termios()
1181 cr2 = stm32_port->swap ? USART_CR2_SWAP : 0; in stm32_usart_set_termios()
1184 cr3 = readl_relaxed(port->membase + ofs->cr3); in stm32_usart_set_termios()
1186 if (stm32_port->fifoen) { in stm32_usart_set_termios()
1187 if (stm32_port->txftcfg >= 0) in stm32_usart_set_termios()
1188 cr3 |= stm32_port->txftcfg << USART_CR3_TXFTCFG_SHIFT; in stm32_usart_set_termios()
1189 if (stm32_port->rxftcfg >= 0) in stm32_usart_set_termios()
1190 cr3 |= stm32_port->rxftcfg << USART_CR3_RXFTCFG_SHIFT; in stm32_usart_set_termios()
1197 stm32_port->rdr_mask = (BIT(bits) - 1); in stm32_usart_set_termios()
1213 } else if ((bits == 7) && cfg->has_7bits_data) { in stm32_usart_set_termios()
1216 dev_dbg(port->dev, "Unsupported data bits config: %u bits\n" in stm32_usart_set_termios()
1220 termios->c_cflag = cflag; in stm32_usart_set_termios()
1228 if (ofs->rtor != UNDEF_REG && (stm32_port->rx_ch || in stm32_usart_set_termios()
1229 (stm32_port->fifoen && in stm32_usart_set_termios()
1230 stm32_port->rxftcfg >= 0))) { in stm32_usart_set_termios()
1237 stm32_port->cr1_irq = USART_CR1_RTOIE; in stm32_usart_set_termios()
1238 writel_relaxed(bits, port->membase + ofs->rtor); in stm32_usart_set_termios()
1242 * wake up over usart, from low power until the DMA gets re-enabled by resume. in stm32_usart_set_termios()
1244 stm32_port->cr3_irq = USART_CR3_RXFTIE; in stm32_usart_set_termios()
1247 cr1 |= stm32_port->cr1_irq; in stm32_usart_set_termios()
1248 cr3 |= stm32_port->cr3_irq; in stm32_usart_set_termios()
1253 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); in stm32_usart_set_termios()
1255 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; in stm32_usart_set_termios()
1259 usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud); in stm32_usart_set_termios()
1270 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_OVER8); in stm32_usart_set_termios()
1274 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_OVER8); in stm32_usart_set_termios()
1279 writel_relaxed(mantissa | fraction, port->membase + ofs->brr); in stm32_usart_set_termios()
1283 port->read_status_mask = USART_SR_ORE; in stm32_usart_set_termios()
1284 if (termios->c_iflag & INPCK) in stm32_usart_set_termios()
1285 port->read_status_mask |= USART_SR_PE | USART_SR_FE; in stm32_usart_set_termios()
1286 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) in stm32_usart_set_termios()
1287 port->read_status_mask |= USART_SR_FE; in stm32_usart_set_termios()
1290 port->ignore_status_mask = 0; in stm32_usart_set_termios()
1291 if (termios->c_iflag & IGNPAR) in stm32_usart_set_termios()
1292 port->ignore_status_mask = USART_SR_PE | USART_SR_FE; in stm32_usart_set_termios()
1293 if (termios->c_iflag & IGNBRK) { in stm32_usart_set_termios()
1294 port->ignore_status_mask |= USART_SR_FE; in stm32_usart_set_termios()
1299 if (termios->c_iflag & IGNPAR) in stm32_usart_set_termios()
1300 port->ignore_status_mask |= USART_SR_ORE; in stm32_usart_set_termios()
1304 if ((termios->c_cflag & CREAD) == 0) in stm32_usart_set_termios()
1305 port->ignore_status_mask |= USART_SR_DUMMY_RX; in stm32_usart_set_termios()
1307 if (stm32_port->rx_ch) { in stm32_usart_set_termios()
1318 if (stm32_port->tx_ch) in stm32_usart_set_termios()
1321 if (rs485conf->flags & SER_RS485_ENABLED) { in stm32_usart_set_termios()
1323 rs485conf->delay_rts_before_send, in stm32_usart_set_termios()
1324 rs485conf->delay_rts_after_send, in stm32_usart_set_termios()
1326 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { in stm32_usart_set_termios()
1328 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND; in stm32_usart_set_termios()
1331 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND; in stm32_usart_set_termios()
1340 if (stm32_port->wakeup_src) { in stm32_usart_set_termios()
1345 writel_relaxed(cr3, port->membase + ofs->cr3); in stm32_usart_set_termios()
1346 writel_relaxed(cr2, port->membase + ofs->cr2); in stm32_usart_set_termios()
1347 writel_relaxed(cr1, port->membase + ofs->cr1); in stm32_usart_set_termios()
1349 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); in stm32_usart_set_termios()
1350 spin_unlock_irqrestore(&port->lock, flags); in stm32_usart_set_termios()
1353 if (UART_ENABLE_MS(port, termios->c_cflag)) in stm32_usart_set_termios()
1361 return (port->type == PORT_STM32) ? DRIVER_NAME : NULL; in stm32_usart_type()
1376 port->type = PORT_STM32; in stm32_usart_config_port()
1383 return -EINVAL; in stm32_usart_verify_port()
1391 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; in stm32_usart_pm()
1392 const struct stm32_usart_config *cfg = &stm32port->info->cfg; in stm32_usart_pm()
1397 pm_runtime_get_sync(port->dev); in stm32_usart_pm()
1400 spin_lock_irqsave(&port->lock, flags); in stm32_usart_pm()
1401 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); in stm32_usart_pm()
1402 spin_unlock_irqrestore(&port->lock, flags); in stm32_usart_pm()
1403 pm_runtime_put_sync(port->dev); in stm32_usart_pm()
1415 return clk_prepare_enable(stm32_port->clk); in stm32_usart_poll_init()
1421 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_poll_get_char()
1423 if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_RXNE)) in stm32_usart_poll_get_char()
1426 return readl_relaxed(port->membase + ofs->rdr) & stm32_port->rdr_mask; in stm32_usart_poll_get_char()
1464 * STM32H7 RX & TX FIFO threshold configuration (CR3 RXFTCFG / TXFTCFG)
1477 if (of_property_read_u32(pdev->dev.of_node, p, &bytes)) in stm32_usart_get_ftcfg()
1484 i = ARRAY_SIZE(stm32h7_usart_fifo_thresh_cfg) - 1; in stm32_usart_get_ftcfg()
1486 dev_dbg(&pdev->dev, "%s set to %d bytes\n", p, in stm32_usart_get_ftcfg()
1491 *ftcfg = i - 1; in stm32_usart_get_ftcfg()
1493 *ftcfg = -EINVAL; in stm32_usart_get_ftcfg()
1498 clk_disable_unprepare(stm32port->clk); in stm32_usart_deinit_port()
1511 struct uart_port *port = &stm32port->port; in stm32_usart_init_port()
1519 port->iotype = UPIO_MEM; in stm32_usart_init_port()
1520 port->flags = UPF_BOOT_AUTOCONF; in stm32_usart_init_port()
1521 port->ops = &stm32_uart_ops; in stm32_usart_init_port()
1522 port->dev = &pdev->dev; in stm32_usart_init_port()
1523 port->fifosize = stm32port->info->cfg.fifosize; in stm32_usart_init_port()
1524 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_STM32_CONSOLE); in stm32_usart_init_port()
1525 port->irq = irq; in stm32_usart_init_port()
1526 port->rs485_config = stm32_usart_config_rs485; in stm32_usart_init_port()
1527 port->rs485_supported = stm32_rs485_supported; in stm32_usart_init_port()
1533 stm32port->wakeup_src = stm32port->info->cfg.has_wakeup && in stm32_usart_init_port()
1534 of_property_read_bool(pdev->dev.of_node, "wakeup-source"); in stm32_usart_init_port()
1536 stm32port->swap = stm32port->info->cfg.has_swap && in stm32_usart_init_port()
1537 of_property_read_bool(pdev->dev.of_node, "rx-tx-swap"); in stm32_usart_init_port()
1539 stm32port->fifoen = stm32port->info->cfg.has_fifo; in stm32_usart_init_port()
1540 if (stm32port->fifoen) { in stm32_usart_init_port()
1541 stm32_usart_get_ftcfg(pdev, "rx-threshold", in stm32_usart_init_port()
1542 &stm32port->rxftcfg); in stm32_usart_init_port()
1543 stm32_usart_get_ftcfg(pdev, "tx-threshold", in stm32_usart_init_port()
1544 &stm32port->txftcfg); in stm32_usart_init_port()
1547 port->membase = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in stm32_usart_init_port()
1548 if (IS_ERR(port->membase)) in stm32_usart_init_port()
1549 return PTR_ERR(port->membase); in stm32_usart_init_port()
1550 port->mapbase = res->start; in stm32_usart_init_port()
1552 spin_lock_init(&port->lock); in stm32_usart_init_port()
1554 stm32port->clk = devm_clk_get(&pdev->dev, NULL); in stm32_usart_init_port()
1555 if (IS_ERR(stm32port->clk)) in stm32_usart_init_port()
1556 return PTR_ERR(stm32port->clk); in stm32_usart_init_port()
1559 ret = clk_prepare_enable(stm32port->clk); in stm32_usart_init_port()
1563 stm32port->port.uartclk = clk_get_rate(stm32port->clk); in stm32_usart_init_port()
1564 if (!stm32port->port.uartclk) { in stm32_usart_init_port()
1565 ret = -EINVAL; in stm32_usart_init_port()
1569 stm32port->gpios = mctrl_gpio_init(&stm32port->port, 0); in stm32_usart_init_port()
1570 if (IS_ERR(stm32port->gpios)) { in stm32_usart_init_port()
1571 ret = PTR_ERR(stm32port->gpios); in stm32_usart_init_port()
1576 * Both CTS/RTS gpios and "st,hw-flow-ctrl" (deprecated) or "uart-has-rtscts" in stm32_usart_init_port()
1579 if (stm32port->hw_flow_control) { in stm32_usart_init_port()
1580 if (mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_CTS) || in stm32_usart_init_port()
1581 mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_RTS)) { in stm32_usart_init_port()
1582 dev_err(&pdev->dev, "Conflicting RTS/CTS config\n"); in stm32_usart_init_port()
1583 ret = -EINVAL; in stm32_usart_init_port()
1591 clk_disable_unprepare(stm32port->clk); in stm32_usart_init_port()
1598 struct device_node *np = pdev->dev.of_node; in stm32_usart_of_get_port()
1606 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", id); in stm32_usart_of_get_port()
1614 of_property_read_bool (np, "st,hw-flow-ctrl") /*deprecated*/ || in stm32_usart_of_get_port()
1615 of_property_read_bool (np, "uart-has-rtscts"); in stm32_usart_of_get_port()
1625 { .compatible = "st,stm32-uart", .data = &stm32f4_info},
1626 { .compatible = "st,stm32f7-uart", .data = &stm32f7_info},
1627 { .compatible = "st,stm32h7-uart", .data = &stm32h7_info},
1637 if (stm32port->rx_buf) in stm32_usart_of_dma_rx_remove()
1638 dma_free_coherent(&pdev->dev, RX_BUF_L, stm32port->rx_buf, in stm32_usart_of_dma_rx_remove()
1639 stm32port->rx_dma_buf); in stm32_usart_of_dma_rx_remove()
1645 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; in stm32_usart_of_dma_rx_probe()
1646 struct uart_port *port = &stm32port->port; in stm32_usart_of_dma_rx_probe()
1647 struct device *dev = &pdev->dev; in stm32_usart_of_dma_rx_probe()
1651 stm32port->rx_buf = dma_alloc_coherent(dev, RX_BUF_L, in stm32_usart_of_dma_rx_probe()
1652 &stm32port->rx_dma_buf, in stm32_usart_of_dma_rx_probe()
1654 if (!stm32port->rx_buf) in stm32_usart_of_dma_rx_probe()
1655 return -ENOMEM; in stm32_usart_of_dma_rx_probe()
1659 config.src_addr = port->mapbase + ofs->rdr; in stm32_usart_of_dma_rx_probe()
1662 ret = dmaengine_slave_config(stm32port->rx_ch, &config); in stm32_usart_of_dma_rx_probe()
1675 if (stm32port->tx_buf) in stm32_usart_of_dma_tx_remove()
1676 dma_free_coherent(&pdev->dev, TX_BUF_L, stm32port->tx_buf, in stm32_usart_of_dma_tx_remove()
1677 stm32port->tx_dma_buf); in stm32_usart_of_dma_tx_remove()
1683 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; in stm32_usart_of_dma_tx_probe()
1684 struct uart_port *port = &stm32port->port; in stm32_usart_of_dma_tx_probe()
1685 struct device *dev = &pdev->dev; in stm32_usart_of_dma_tx_probe()
1689 stm32port->tx_buf = dma_alloc_coherent(dev, TX_BUF_L, in stm32_usart_of_dma_tx_probe()
1690 &stm32port->tx_dma_buf, in stm32_usart_of_dma_tx_probe()
1692 if (!stm32port->tx_buf) in stm32_usart_of_dma_tx_probe()
1693 return -ENOMEM; in stm32_usart_of_dma_tx_probe()
1697 config.dst_addr = port->mapbase + ofs->tdr; in stm32_usart_of_dma_tx_probe()
1700 ret = dmaengine_slave_config(stm32port->tx_ch, &config); in stm32_usart_of_dma_tx_probe()
1717 return -ENODEV; in stm32_usart_serial_probe()
1719 stm32port->info = of_device_get_match_data(&pdev->dev); in stm32_usart_serial_probe()
1720 if (!stm32port->info) in stm32_usart_serial_probe()
1721 return -EINVAL; in stm32_usart_serial_probe()
1723 stm32port->rx_ch = dma_request_chan(&pdev->dev, "rx"); in stm32_usart_serial_probe()
1724 if (PTR_ERR(stm32port->rx_ch) == -EPROBE_DEFER) in stm32_usart_serial_probe()
1725 return -EPROBE_DEFER; in stm32_usart_serial_probe()
1727 /* Fall back in interrupt mode for any non-deferral error */ in stm32_usart_serial_probe()
1728 if (IS_ERR(stm32port->rx_ch)) in stm32_usart_serial_probe()
1729 stm32port->rx_ch = NULL; in stm32_usart_serial_probe()
1731 stm32port->tx_ch = dma_request_chan(&pdev->dev, "tx"); in stm32_usart_serial_probe()
1732 if (PTR_ERR(stm32port->tx_ch) == -EPROBE_DEFER) { in stm32_usart_serial_probe()
1733 ret = -EPROBE_DEFER; in stm32_usart_serial_probe()
1736 /* Fall back in interrupt mode for any non-deferral error */ in stm32_usart_serial_probe()
1737 if (IS_ERR(stm32port->tx_ch)) in stm32_usart_serial_probe()
1738 stm32port->tx_ch = NULL; in stm32_usart_serial_probe()
1744 if (stm32port->wakeup_src) { in stm32_usart_serial_probe()
1745 device_set_wakeup_capable(&pdev->dev, true); in stm32_usart_serial_probe()
1746 ret = dev_pm_set_wake_irq(&pdev->dev, stm32port->port.irq); in stm32_usart_serial_probe()
1751 if (stm32port->rx_ch && stm32_usart_of_dma_rx_probe(stm32port, pdev)) { in stm32_usart_serial_probe()
1753 dma_release_channel(stm32port->rx_ch); in stm32_usart_serial_probe()
1754 stm32port->rx_ch = NULL; in stm32_usart_serial_probe()
1757 if (stm32port->tx_ch && stm32_usart_of_dma_tx_probe(stm32port, pdev)) { in stm32_usart_serial_probe()
1759 dma_release_channel(stm32port->tx_ch); in stm32_usart_serial_probe()
1760 stm32port->tx_ch = NULL; in stm32_usart_serial_probe()
1763 if (!stm32port->rx_ch) in stm32_usart_serial_probe()
1764 dev_info(&pdev->dev, "interrupt mode for rx (no dma)\n"); in stm32_usart_serial_probe()
1765 if (!stm32port->tx_ch) in stm32_usart_serial_probe()
1766 dev_info(&pdev->dev, "interrupt mode for tx (no dma)\n"); in stm32_usart_serial_probe()
1768 platform_set_drvdata(pdev, &stm32port->port); in stm32_usart_serial_probe()
1770 pm_runtime_get_noresume(&pdev->dev); in stm32_usart_serial_probe()
1771 pm_runtime_set_active(&pdev->dev); in stm32_usart_serial_probe()
1772 pm_runtime_enable(&pdev->dev); in stm32_usart_serial_probe()
1774 ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port); in stm32_usart_serial_probe()
1778 pm_runtime_put_sync(&pdev->dev); in stm32_usart_serial_probe()
1783 pm_runtime_disable(&pdev->dev); in stm32_usart_serial_probe()
1784 pm_runtime_set_suspended(&pdev->dev); in stm32_usart_serial_probe()
1785 pm_runtime_put_noidle(&pdev->dev); in stm32_usart_serial_probe()
1787 if (stm32port->tx_ch) in stm32_usart_serial_probe()
1789 if (stm32port->rx_ch) in stm32_usart_serial_probe()
1792 if (stm32port->wakeup_src) in stm32_usart_serial_probe()
1793 dev_pm_clear_wake_irq(&pdev->dev); in stm32_usart_serial_probe()
1796 if (stm32port->wakeup_src) in stm32_usart_serial_probe()
1797 device_set_wakeup_capable(&pdev->dev, false); in stm32_usart_serial_probe()
1802 if (stm32port->tx_ch) in stm32_usart_serial_probe()
1803 dma_release_channel(stm32port->tx_ch); in stm32_usart_serial_probe()
1806 if (stm32port->rx_ch) in stm32_usart_serial_probe()
1807 dma_release_channel(stm32port->rx_ch); in stm32_usart_serial_probe()
1816 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_serial_remove()
1819 pm_runtime_get_sync(&pdev->dev); in stm32_usart_serial_remove()
1822 pm_runtime_disable(&pdev->dev); in stm32_usart_serial_remove()
1823 pm_runtime_set_suspended(&pdev->dev); in stm32_usart_serial_remove()
1824 pm_runtime_put_noidle(&pdev->dev); in stm32_usart_serial_remove()
1826 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_PEIE); in stm32_usart_serial_remove()
1828 if (stm32_port->tx_ch) { in stm32_usart_serial_remove()
1830 dma_release_channel(stm32_port->tx_ch); in stm32_usart_serial_remove()
1833 if (stm32_port->rx_ch) { in stm32_usart_serial_remove()
1835 dma_release_channel(stm32_port->rx_ch); in stm32_usart_serial_remove()
1838 cr3 = readl_relaxed(port->membase + ofs->cr3); in stm32_usart_serial_remove()
1843 writel_relaxed(cr3, port->membase + ofs->cr3); in stm32_usart_serial_remove()
1845 if (stm32_port->wakeup_src) { in stm32_usart_serial_remove()
1846 dev_pm_clear_wake_irq(&pdev->dev); in stm32_usart_serial_remove()
1847 device_init_wakeup(&pdev->dev, false); in stm32_usart_serial_remove()
1858 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_console_putchar()
1862 ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr, isr, in stm32_usart_console_putchar()
1866 dev_err(port->dev, "Error while sending data in UART TX : %d\n", ret); in stm32_usart_console_putchar()
1869 writel_relaxed(ch, port->membase + ofs->tdr); in stm32_usart_console_putchar()
1876 struct uart_port *port = &stm32_ports[co->index].port; in stm32_usart_console_write()
1878 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_console_write()
1879 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; in stm32_usart_console_write()
1885 locked = spin_trylock_irqsave(&port->lock, flags); in stm32_usart_console_write()
1887 spin_lock_irqsave(&port->lock, flags); in stm32_usart_console_write()
1890 old_cr1 = readl_relaxed(port->membase + ofs->cr1); in stm32_usart_console_write()
1892 new_cr1 |= USART_CR1_TE | BIT(cfg->uart_enable_bit); in stm32_usart_console_write()
1893 writel_relaxed(new_cr1, port->membase + ofs->cr1); in stm32_usart_console_write()
1898 writel_relaxed(old_cr1, port->membase + ofs->cr1); in stm32_usart_console_write()
1901 spin_unlock_irqrestore(&port->lock, flags); in stm32_usart_console_write()
1912 if (co->index >= STM32_MAX_PORTS) in stm32_usart_console_setup()
1913 return -ENODEV; in stm32_usart_console_setup()
1915 stm32port = &stm32_ports[co->index]; in stm32_usart_console_setup()
1920 * this to be called during the uart port registration when the in stm32_usart_console_setup()
1923 if (stm32port->port.mapbase == 0 || !stm32port->port.membase) in stm32_usart_console_setup()
1924 return -ENXIO; in stm32_usart_console_setup()
1929 return uart_set_options(&stm32port->port, co, baud, parity, bits, flow); in stm32_usart_console_setup()
1938 .index = -1,
1951 struct stm32_usart_info *info = port->private_data; in early_stm32_usart_console_putchar()
1953 while (!(readl_relaxed(port->membase + info->ofs.isr) & USART_SR_TXE)) in early_stm32_usart_console_putchar()
1956 writel_relaxed(ch, port->membase + info->ofs.tdr); in early_stm32_usart_console_putchar()
1961 struct earlycon_device *device = console->data; in early_stm32_serial_write()
1962 struct uart_port *port = &device->port; in early_stm32_serial_write()
1969 if (!(device->port.membase || device->port.iobase)) in early_stm32_h7_serial_setup()
1970 return -ENODEV; in early_stm32_h7_serial_setup()
1971 device->port.private_data = &stm32h7_info; in early_stm32_h7_serial_setup()
1972 device->con->write = early_stm32_serial_write; in early_stm32_h7_serial_setup()
1978 if (!(device->port.membase || device->port.iobase)) in early_stm32_f7_serial_setup()
1979 return -ENODEV; in early_stm32_f7_serial_setup()
1980 device->port.private_data = &stm32f7_info; in early_stm32_f7_serial_setup()
1981 device->con->write = early_stm32_serial_write; in early_stm32_f7_serial_setup()
1987 if (!(device->port.membase || device->port.iobase)) in early_stm32_f4_serial_setup()
1988 return -ENODEV; in early_stm32_f4_serial_setup()
1989 device->port.private_data = &stm32f4_info; in early_stm32_f4_serial_setup()
1990 device->con->write = early_stm32_serial_write; in early_stm32_f4_serial_setup()
1994 OF_EARLYCON_DECLARE(stm32, "st,stm32h7-uart", early_stm32_h7_serial_setup);
1995 OF_EARLYCON_DECLARE(stm32, "st,stm32f7-uart", early_stm32_f7_serial_setup);
1996 OF_EARLYCON_DECLARE(stm32, "st,stm32-uart", early_stm32_f4_serial_setup);
2012 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_serial_en_wakeup()
2013 struct tty_port *tport = &port->state->port; in stm32_usart_serial_en_wakeup()
2018 if (!stm32_port->wakeup_src || !tty_port_initialized(tport)) in stm32_usart_serial_en_wakeup()
2022 * Enable low-power wake-up and wake-up irq if argument is set to in stm32_usart_serial_en_wakeup()
2023 * "enable", disable low-power wake-up and wake-up irq otherwise in stm32_usart_serial_en_wakeup()
2026 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_UESM); in stm32_usart_serial_en_wakeup()
2027 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_WUFIE); in stm32_usart_serial_en_wakeup()
2028 mctrl_gpio_enable_irq_wake(stm32_port->gpios); in stm32_usart_serial_en_wakeup()
2032 * entering low-power mode and re-enabled when exiting from in stm32_usart_serial_en_wakeup()
2033 * low-power mode. in stm32_usart_serial_en_wakeup()
2035 if (stm32_port->rx_ch) { in stm32_usart_serial_en_wakeup()
2036 spin_lock_irqsave(&port->lock, flags); in stm32_usart_serial_en_wakeup()
2049 if (stm32_port->rx_ch) { in stm32_usart_serial_en_wakeup()
2054 mctrl_gpio_disable_irq_wake(stm32_port->gpios); in stm32_usart_serial_en_wakeup()
2055 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_UESM); in stm32_usart_serial_en_wakeup()
2056 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_WUFIE); in stm32_usart_serial_en_wakeup()
2113 clk_disable_unprepare(stm32port->clk); in stm32_usart_runtime_suspend()
2124 return clk_prepare_enable(stm32port->clk); in stm32_usart_runtime_resume()