Lines Matching +full:36 +full:- +full:41
1 /* SPDX-License-Identifier: GPL-2.0 */
40 #define CLK_MOUT_SCLK_MMC0_C 36
45 #define CLK_MOUT_SCLK_UART2 41
237 #define CLK_MOUT_SCLK_DECON_TV_ECLK_A 36
242 #define CLK_MOUT_SCLK_DSIM0_B 41
431 #define CLK_SCLK_UART0 36
436 #define CLK_PCLK_SCI 41
501 #define CLK_SCLK_SECKEY 36
506 #define CLK_SCLK_OTP_CON 41
544 #define CLK_PHYCLK_UFS_RX1_SYMBOL_PHY 36
678 #define CLK_DIV_PCLK_DISP 36
681 #define CLK_ACLK_DECON 41
798 #define CLK_PCLK_TIMER 36
803 #define CLK_SCLK_JTAG_TCK 41
953 #define CLK_PCLK_DBG_CSSYS 36
1073 #define CLK_ACLK_SMMU_SCALERC 36
1078 #define CLK_ACLK_BTS_DIS1 41
1154 #define CLK_DIV_ACLK_LITE_B 36
1159 #define CLK_DIV_PCLK_3AA1 41
1291 #define CLK_ACLK_ASYNCAXIS_CA5 36
1296 #define CLK_ACLK_ASYNCAXIM_ISP3P 41