Lines Matching +full:36 +full:- +full:41
1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
4 * Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
48 #define CLK_TOP_PWRAP_ULPOSC 36
53 #define CLK_TOP_DPI 41
297 #define CLK_INFRA_AO_MSDC1_SRC 36
302 #define CLK_INFRA_AO_DEBUGSYS 41
469 #define CLK_VPP0_MDP_COLOR 36
474 #define CLK_VPP0_WARP1_MDP_DL_ASYNC 41
580 #define CLK_VPP1_SVPP2_MDP_RSZ 36
585 #define CLK_VPP1_SVPP3_MDP_TDSHP 41
799 #define CLK_VDO0_SMI_GALS 36
804 #define CLK_VDO0_SMI_RSI 41
848 #define CLK_VDO1_HDR_GFX_FE1 36
853 #define CLK_VDO1_HDR_GFX_FE1_DL_ASYNC 41