Lines Matching +full:0 +full:x03d0

24 /* main registers, BAR0 + 0x0000 */
26 	/* offset 0x0000 */
36 #define     M8051_RESET                                         0
47 #define     EEPROM_WRITE_DATA                                   0
50 	/* offset 0x0010 */
60 #define     ENDPOINT_0_INTERRUPT_ENABLE                         0
83 #define     SOF_INTERRUPT_ENABLE                                0
92 #define     ENDPOINT_0_INTERRUPT_ENABLE                         0
118 #define     SOF_INTERRUPT_ENABLE                                0
120 	/* offset 0x0020 */
147 #define     SOF_INTERRUPT_ENABLE                                0
157 #define     ENDPOINT_0_INTERRUPT                                0
158 #define     USB3380_IRQSTAT0_EP_INTR_MASK_IN (0xF << 17)
159 #define     USB3380_IRQSTAT0_EP_INTR_MASK_OUT (0xF << 1)
186 #define     SOF_INTERRUPT                                       0
187 	/* offset 0x0030 */
194 #define     FIFO_CONFIGURATION_SELECT                           0
196 	/* offset 0x0040 */
201 #define     MEMORY_ADDRESS                                      0
205 	/* offset 0x0050 */
219 #define     GPIO0_DATA                                          0
224 #define     GPIO0_INTERRUPT                                     0
227 /* usb control, BAR0 + 0x0080 */
229 	/* offset 0x0080 */
247 #define     GET_DEVICE_STATUS                                   0
250 #define     VENDOR_ID                                           0
266 #define     SELF_POWERED_STATUS                                 0
267 	/* offset 0x0090 */
280 #define     TERMINATION_SELECT                                  0
283 	/* offset 0x0090 */
287 #define     OUR_USB_ADDRESS                                     0
291 /* pci control, BAR0 + 0x0100 */
293 	/* offset 0x0100 */
302 #define         MEM_READ_OR_WRITE                                   0
307 #define         PCI_MASTER_WRITE                                    0
309 #define     PCI_MASTER_BYTE_WRITE_ENABLES                       0
315 #define     PCI_HOST_MODE                                       0
318 /* dma control, BAR0 + 0x0180 ... array of four structs like this,
319  * for channels 0..3.  see also struct net2280_dma:  descriptor
323 	/* offset 0x0180, 0x01a0, 0x01c0, 0x01e0, */
328 #define         POLL_CONTINUOUS                                     0
339 #define     DMA_ADDRESS_HOLD                                    0
345 #define     DMA_START                                           0
347 	/* offset 0x0190, 0x01b0, 0x01d0, 0x01f0, */
354 #define     DMA_BYTE_COUNT                                      0
360 /* dedicated endpoint registers, BAR0 + 0x0200 */
363 	/* offset 0x0200, 0x0210, 0x220, 0x230, 0x240 */
365 	/* offset 0x0204, 0x0214, 0x224, 0x234, 0x244 */
370 /* configurable endpoint registers, BAR0 + 0x0300 ... array of seven structs
375 	/* offset 0x0300, 0x0320, 0x0340, 0x0360, 0x0380, 0x03a0, 0x03c0 */
381 #define     ENDPOINT_NUMBER                                     0
398 #define     CLEAR_ENDPOINT_HALT                                 0
405 #define     DATA_IN_TOKEN_INTERRUPT_ENABLE                      0
426 #define     DATA_IN_TOKEN_INTERRUPT                             0
427 	/* offset 0x0310, 0x0330, 0x0350, 0x0370, 0x0390, 0x03b0, 0x03d0 */