Lines Matching +full:buffer +full:- +full:enable
1 // SPDX-License-Identifier: GPL-2.0
124 #define XTAL 0xC000 /* b15-14: Crystal selection */
128 #define XCKE 0x2000 /* b13: External clock enable */
130 #define SCKE 0x0400 /* b10: USB clock enable */
133 #define HSE 0x0080 /* b7: Hi-speed enable */
135 #define DRPD 0x0020 /* b5: D+/- pull down control */
137 #define USBE 0x0001 /* b0: USB module operation enable */
140 #define OVCBIT 0x8000 /* b15-14: Over-current bit */
141 #define OVCMON 0xC000 /* b15-14: Over-current monitor */
143 #define IDMON 0x0004 /* b3: ID-pin monitor */
144 #define LNST 0x0003 /* b1-0: D+, D- line status */
146 #define FS_KSTS 0x0002 /* Full-Speed K State */
147 #define FS_JSTS 0x0001 /* Full-Speed J State */
148 #define LS_JSTS 0x0002 /* Low-Speed J State */
149 #define LS_KSTS 0x0001 /* Low-Speed K State */
157 #define USBRST 0x0040 /* b6: USB reset enable */
158 #define RESUME 0x0020 /* b5: Resume enable */
159 #define UACT 0x0010 /* b4: USB bus enable */
160 #define RHST 0x0007 /* b1-0: Reset handshake status */
162 #define HSMODE 0x0003 /* Hi-Speed mode */
163 #define FSMODE 0x0002 /* Full-Speed mode */
164 #define LSMODE 0x0001 /* Low-Speed mode */
168 #define UTST 0x000F /* b3-0: Test select */
184 #define INTA 0x0001 /* b1: USB INT-pin active */
190 #define DFORM 0x0380 /* b9-7: DMA mode select */
197 #define DENDE 0x0010 /* b4: Dend enable */
202 #define REW 0x4000 /* b14: Buffer rewind */
203 #define DCLRM 0x2000 /* b13: DMA buffer clear mode */
204 #define DREQE 0x1000 /* b12: DREQ output enable */
212 #define CURPIPE 0x000F /* b2-0: PIPE select */
215 #define BVAL 0x8000 /* b15: Buffer valid flag */
216 #define BCLR 0x4000 /* b14: Buffer clear */
218 #define DTLN 0x0FFF /* b11-0: FIFO received data length */
220 /* Interrupt Enable Register 0 */
226 #define BEMPE 0x0400 /* b10: Buffer empty interrupt */
227 #define NRDYE 0x0200 /* b9: Buffer not ready interrupt */
228 #define BRDYE 0x0100 /* b8: Buffer ready interrupt */
230 /* Interrupt Enable Register 1 */
231 #define OVRCRE 0x8000 /* b15: Over-current interrupt */
239 /* BRDY Interrupt Enable/Status Register */
251 /* NRDY Interrupt Enable/Status Register */
263 /* BEMP Interrupt Enable/Status Register */
276 #define TRNENSEL 0x0100 /* b8: Select transaction enable period */
280 #define SOFMODE 0x000C /* b3-2: SOF pin select */
291 #define BEMP 0x0400 /* b10: Buffer empty interrupt */
292 #define NRDY 0x0200 /* b9: Buffer not ready interrupt */
293 #define BRDY 0x0100 /* b8: Buffer ready interrupt */
295 #define DVSQ 0x0070 /* b6-4: Device state */
305 #define DVSQS 0x0030 /* b5-4: Device state */
307 #define CTSQ 0x0007 /* b2-0: Control transfer stage */
317 #define OVRCR 0x8000 /* b15: Over-current interrupt */
321 #define EOFERR 0x0040 /* b6: EOF-error interrupt */
328 #define FRNM 0x07FF /* b10-0: Frame number */
331 #define UFRNM 0x0007 /* b2-0: Micro frame number */
335 #define DEVSEL 0xF000 /* b15-14: Device address select */
336 #define MAXP 0x007F /* b6-0: Maxpacket size of default control pipe */
339 #define BSTS 0x8000 /* b15: Buffer status */
341 #define CSCLR 0x2000 /* b13: complete-split status clear */
342 #define CSSTS 0x1000 /* b12: complete-split status */
348 #define PINGE 0x0010 /* b4: ping enable */
349 #define CCPL 0x0004 /* b2: Enable control transfer complete */
350 #define PID 0x0003 /* b1-0: Response PID */
357 #define PIPENM 0x0007 /* b2-0: Pipe select */
360 #define R8A66597_TYP 0xC000 /* b15-14: Transfer type */
364 #define R8A66597_BFRE 0x0400 /* b10: Buffer ready interrupt mode select */
365 #define R8A66597_DBLB 0x0200 /* b9: Double buffer mode select */
369 #define R8A66597_EPNUM 0x000F /* b3-0: Eendpoint number select */
371 /* Pipe Buffer Configuration Register */
372 #define BUFSIZE 0x7C00 /* b14-10: Pipe buffer size */
373 #define BUFNMB 0x007F /* b6-0: Pipe buffer number */
378 #define MXPS 0x07FF /* b10-0: Maxpacket size */
381 #define IFIS 0x1000 /* b12: Isochronous in-buffer flush mode select */
382 #define IITV 0x0007 /* b2-0: Isochronous interval */
385 #define BSTS 0x8000 /* b15: Buffer status */
386 #define INBUFM 0x4000 /* b14: IN buffer monitor (Only for PIPE1 to 5) */
387 #define CSCLR 0x2000 /* b13: complete-split status clear */
388 #define CSSTS 0x1000 /* b12: complete-split status */
390 #define ACLRM 0x0200 /* b9: Out buffer auto clear mode */
395 #define PID 0x0003 /* b1-0: Response PID */
398 #define TRENB 0x0200 /* b9: Transaction counter enable */
402 #define TRNCNT 0xFFFF /* b15-0: Transaction counter */
432 #define SENDBUFM 0x1000 /* b12: Transmit Buffer Mode */
434 #define LBA_WAIT 0x0030 /* b5-4: Local Bus Access Wait */
436 /* DMA Enable Registers */
437 #define DEN 0x0001 /* b1: DMA Transfer Enable */
443 /* DMA Buffer Control Register */
444 #define CH1BUFW 0x0200 /* b9: Ch1 DMA Buffer Data Transfer Enable */
445 #define CH0BUFW 0x0100 /* b8: Ch0 DMA Buffer Data Transfer Enable */
446 #define CH1BUFS 0x0002 /* b2: Ch1 DMA Buffer Data Status */
447 #define CH0BUFS 0x0001 /* b1: Ch0 DMA Buffer Data Status */
450 #define CH1ERRE 0x0200 /* b9: Ch1 SHwy Res Err Detect Int Enable */
451 #define CH0ERRE 0x0100 /* b8: Ch0 SHwy Res Err Detect Int Enable */
452 #define CH1ENDE 0x0002 /* b2: Ch1 DMA Transfer End Int Enable */
453 #define CH0ENDE 0x0001 /* b1: Ch0 DMA Transfer End Int Enable */