Lines Matching +full:0 +full:x5f0
15 #define DDR3PHY_PIR (0x04) /* DDR3PHY PHY Initialization Register */
20 #define DDR3PHY_PIR_INIT (1 << 0) /* Initialization Trigger */
22 #define DDR3PHY_PGCR (0x08) /* DDR3PHY PHY General Configuration Register */
26 #define DDR3PHY_PGSR (0x0C) /* DDR3PHY PHY General Status Register */
27 #define DDR3PHY_PGSR_IDONE (1 << 0) /* Initialization Done */
29 #define DDR3PHY_ACDLLCR (0x14) /* DDR3PHY AC DLL Control Register */
32 #define DDR3PHY_ACIOCR (0x24) /* DDR3PHY AC I/O Configuration Register */
33 #define DDR3PHY_ACIOCR_CSPDD_CS0 (1 << 18) /* CS#[0] Power Down Driver */
34 #define DDR3PHY_ACIOCR_CKPDD_CK0 (1 << 8) /* CK[0] Power Down Driver */
37 #define DDR3PHY_DXCCR (0x28) /* DDR3PHY DATX8 Common Configuration Register */
40 #define DDR3PHY_DSGCR (0x2C) /* DDR3PHY DDR System General Configuration Register */
41 #define DDR3PHY_DSGCR_ODTPDD_ODT0 (1 << 20) /* ODT[0] Power Down Driver */
43 #define DDR3PHY_ZQ0SR0 (0x188) /* ZQ status register 0 */
44 #define DDR3PHY_ZQ0SR0_PDO_OFF (0) /* Pull-down output impedance select offset */
49 #define DDR3PHY_DX0DLLCR (0x1CC) /* DDR3PHY DATX8 DLL Control Register */
50 #define DDR3PHY_DX1DLLCR (0x20C) /* DDR3PHY DATX8 DLL Control Register */
54 #define UDDRC_STAT (0x04) /* UDDRC Operating Mode Status Register */
55 #define UDDRC_STAT_SELFREF_TYPE_DIS (0x0 << 4) /* SDRAM is not in Self-refresh */
56 #define UDDRC_STAT_SELFREF_TYPE_PHY (0x1 << 4) /* SDRAM is in Self-refresh, which was caused by PH…
57 #define UDDRC_STAT_SELFREF_TYPE_SW (0x2 << 4) /* SDRAM is in Self-refresh, which was not caused so…
58 #define UDDRC_STAT_SELFREF_TYPE_AUTO (0x3 << 4) /* SDRAM is in Self-refresh, which was caused by A…
59 #define UDDRC_STAT_SELFREF_TYPE_MSK (0x3 << 4) /* Self-refresh type mask */
60 #define UDDRC_STAT_OPMODE_INIT (0x0 << 0) /* Init */
61 #define UDDRC_STAT_OPMODE_NORMAL (0x1 << 0) /* Normal */
62 #define UDDRC_STAT_OPMODE_PWRDOWN (0x2 << 0) /* Power-down */
63 #define UDDRC_STAT_OPMODE_SELF_REFRESH (0x3 << 0) /* Self-refresh */
64 #define UDDRC_STAT_OPMODE_MSK (0x7 << 0) /* Operating mode mask */
66 #define UDDRC_PWRCTL (0x30) /* UDDRC Low Power Control Register */
67 #define UDDRC_PWRCTL_SELFREF_EN (1 << 0) /* Automatic self-refresh */
70 #define UDDRC_DFIMISC (0x1B0) /* UDDRC DFI Miscellaneous Control Register */
71 #define UDDRC_DFIMISC_DFI_INIT_COMPLETE_EN (1 << 0) /* PHY initialization complete enable signal */
73 #define UDDRC_SWCTRL (0x320) /* UDDRC Software Register Programming Control Enable */
74 #define UDDRC_SWCTRL_SW_DONE (1 << 0) /* Enable quasi-dynamic register programming outside reset …
76 #define UDDRC_SWSTAT (0x324) /* UDDRC Software Register Programming Control Status */
77 #define UDDRC_SWSTAT_SW_DONE_ACK (1 << 0) /* Register programming done */
79 #define UDDRC_PSTAT (0x3FC) /* UDDRC Port Status Register */
80 #define UDDRC_PSTAT_ALL_PORTS (0x1F001F) /* Read + writes outstanding transactions on all ports */
82 #define UDDRC_PCTRL_0 (0x490) /* UDDRC Port 0 Control Register */
83 #define UDDRC_PCTRL_1 (0x540) /* UDDRC Port 1 Control Register */
84 #define UDDRC_PCTRL_2 (0x5F0) /* UDDRC Port 2 Control Register */
85 #define UDDRC_PCTRL_3 (0x6A0) /* UDDRC Port 3 Control Register */
86 #define UDDRC_PCTRL_4 (0x750) /* UDDRC Port 4 Control Register */