448  * the OPCLK divisor is calculated directly, not iteratively.
488 		 * The user needs OPCLK. Choose OPCLKDIV to put  in wm8978_configure_pll()
513 		 * Not using OPCLK, but PLL is used for the codec, choose R:  in wm8978_configure_pll()
553 		/* Output PLL (OPCLK) to GPIO1 */  in wm8978_configure_pll()
576 			 * OPCLK, configure the PLL based on that and start it  in wm8978_set_dai_clkdiv()
577 			 * and OPCLK immediately. We will configure PLL to match  in wm8978_set_dai_clkdiv()
578 			 * user-requested OPCLK frquency as good as possible.  in wm8978_set_dai_clkdiv()
582 			 * must not interrupt OPCLK. But it should be fine,  in wm8978_set_dai_clkdiv()
583 			 * because typically the user will request OPCLK to run  in wm8978_set_dai_clkdiv()
586 			 * be equal to or double the OPCLK divisor.  in wm8978_set_dai_clkdiv()
619 		/* Even if MCLK is used for system clock, might have to drive OPCLK */  in wm8978_set_dai_sysclk()
780 			/* We only enter here, if OPCLK is not used */  in wm8978_hw_params()
789 		/* Either MCLK is used directly, or OPCLK is used */  in wm8978_hw_params()
806 		/* OPCLK not used, codec driven by PLL */  in wm8978_hw_params()
879 		/* Preserve PLL - OPCLK may be used by someone */  in wm8978_set_bias_level()