| /third_party/node/deps/v8/src/regexp/arm64/ |
| D | regexp-macro-assembler-arm64.cc | 322 __ Lsr(x11, GetCachedRegister(start_reg), kWRegSizeInBits); in CheckNotBackReferenceIgnoreCase() local
475 __ Lsr(x11, GetCachedRegister(start_reg), kWRegSizeInBits); in CheckNotBackReference() local
980 __ Lsr(capture_end.X(), capture_start.X(), kWRegSizeInBits); in GetCode() local
1285 __ Lsr(current_input_offset().X(), GetCachedRegister(reg), in ReadCurrentPositionFromRegister() local
1604 __ Lsr(maybe_result.X(), GetCachedRegister(register_index), in GetRegister() local
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| /third_party/vixl/test/aarch64/ |
| D | test-assembler-sve-aarch64.cc | 8533 __ Lsr(x1, x1, 1); in TEST_SVE() local
8542 __ Lsr(x2, x2, 2); in TEST_SVE() local
9527 __ Lsr(z29.VnD(), z28.VnD(), 1); // Shift right to 0x4000000040000000 in TEST_SVE() local
9532 __ Lsr(z29.VnD(), z29.VnD(), 1); // Shift right to 0x2000000020000000 in TEST_SVE() local
9537 __ Lsr(z29.VnD(), z29.VnD(), 1); // Shift right to 0x1000000010000000 in TEST_SVE() local
9721 __ Lsr(z29.VnD(), z28.VnD(), 1); // Shift right to 0x4000000040000000 in TEST_SVE() local
9726 __ Lsr(z29.VnD(), z29.VnD(), 1); // Shift right to 0x2000000020000000 in TEST_SVE() local
9731 __ Lsr(z29.VnD(), z29.VnD(), 1); // Shift right to 0x1000000010000000 in TEST_SVE() local
9898 __ Lsr(zn, zn, shift); in GatherLoadScalarPlusVectorHelper() local
10423 __ Lsr(x1, x1, 1); in TEST_SVE() local
[all …]
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| D | test-utils-aarch64.cc | 974 __ Lsr(t2, t2, 4); in ComputeMachineStateHash() local
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| D | test-assembler-aarch64.cc | 6222 __ Lsr(x16, x0, x1); in TEST() local
6223 __ Lsr(x17, x0, x2); in TEST() local
6224 __ Lsr(x18, x0, x3); in TEST() local
6225 __ Lsr(x19, x0, x4); in TEST() local
6226 __ Lsr(x20, x0, x5); in TEST() local
6227 __ Lsr(x21, x0, x6); in TEST() local
6229 __ Lsr(w22, w0, w1); in TEST() local
6230 __ Lsr(w23, w0, w2); in TEST() local
6231 __ Lsr(w24, w0, w3); in TEST() local
6232 __ Lsr(w25, w0, w4); in TEST() local
[all …]
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| D | macro-assembler-arm64-inl.h | 787 void TurboAssembler::Lsr(const Register& rd, const Register& rn, in Lsr() function
794 void TurboAssembler::Lsr(const Register& rd, const Register& rn, in Lsr() function
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| /third_party/node/deps/v8/src/builtins/arm64/ |
| D | builtins-arm64.cc | 1042 __ Lsr(params_size, params_size, kSystemPointerSizeLog2); in LeaveInterpreterFrame() local
1512 __ Lsr(x11, x11, kSystemPointerSizeLog2); in Generate_InterpreterEntryTrampoline() local
3975 __ Lsr(unwind_limit, unwind_limit, kSystemPointerSizeLog2); in Generate_DeoptimizationEntry() local
4012 __ Lsr(frame_size, x3, kSystemPointerSizeLog2); in Generate_DeoptimizationEntry() local
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| /third_party/vixl/src/aarch64/ |
| D | macro-assembler-aarch64.h | 2159 void Lsr(const Register& rd, const Register& rn, unsigned shift) { in Lsr() function
2166 void Lsr(const Register& rd, const Register& rn, const Register& rm) { in Lsr() function
5382 void Lsr(const ZRegister& zd, in Lsr() function
5394 void Lsr(const ZRegister& zd, const ZRegister& zn, int shift) { in Lsr() function
5399 void Lsr(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) { in Lsr() function
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| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/ |
| D | IceInstARM32.h | 398 Lsr, enumerator
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| /third_party/vixl/test/aarch32/ |
| D | test-assembler-aarch32.cc | 784 __ Lsr(r4, r1, 8); in TEST() local
810 __ Lsr(r4, r1, r9); in TEST() local
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| /third_party/vixl/src/aarch32/ |
| D | macro-assembler-aarch32.h | 2718 void Lsr(Condition cond, Register rd, Register rm, const Operand& operand) { in Assembler() function
2739 void Lsr(Register rd, Register rm, const Operand& operand) { in Assembler() function
2742 void Lsr(FlagsUpdate flags, in Assembler() function
2768 void Lsr(FlagsUpdate flags, in Assembler() function
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