1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * BCM47XX Sonics SiliconBackplane embedded ram core 4 * 5 * Copyright (C) 1999-2019, Broadcom. 6 * 7 * Unless you and Broadcom execute a separate written software license 8 * agreement governing use of this software, this software is licensed to you 9 * under the terms of the GNU General Public License version 2 (the "GPL"), 10 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 11 * following added to such license: 12 * 13 * As a special exception, the copyright holders of this software give you 14 * permission to link this software with independent modules, and to copy and 15 * distribute the resulting executable under terms of your choice, provided that 16 * you also meet, for each linked independent module, the terms and conditions of 17 * the license of that module. An independent module is a module which is not 18 * derived from this software. The special exception does not apply to any 19 * modifications of the software. 20 * 21 * Notwithstanding the above, under no circumstances may you combine this 22 * software in any way with any other Broadcom software provided under a license 23 * other than the GPL, without Broadcom's express prior written consent. 24 * 25 * 26 * <<Broadcom-WL-IPTag/Open:>> 27 * 28 * $Id: sbsocram.h 619629 2016-02-17 18:37:56Z $ 29 */ 30 31 #ifndef _SBSOCRAM_H 32 #define _SBSOCRAM_H 33 34 #ifndef _LANGUAGE_ASSEMBLY 35 36 /* cpp contortions to concatenate w/arg prescan */ 37 #ifndef PAD 38 #define _PADLINE(line) pad ## line 39 #define _XSTR(line) _PADLINE(line) 40 #define PAD _XSTR(__LINE__) 41 #endif /* PAD */ 42 43 /* Memcsocram core registers */ 44 typedef volatile struct sbsocramregs { 45 uint32 coreinfo; 46 uint32 bwalloc; 47 uint32 extracoreinfo; 48 uint32 biststat; 49 uint32 bankidx; 50 uint32 standbyctrl; 51 52 uint32 errlogstatus; /* rev 6 */ 53 uint32 errlogaddr; /* rev 6 */ 54 /* used for patching rev 3 & 5 */ 55 uint32 cambankidx; 56 uint32 cambankstandbyctrl; 57 uint32 cambankpatchctrl; 58 uint32 cambankpatchtblbaseaddr; 59 uint32 cambankcmdreg; 60 uint32 cambankdatareg; 61 uint32 cambankmaskreg; 62 uint32 PAD[1]; 63 uint32 bankinfo; /* corev 8 */ 64 uint32 bankpda; 65 uint32 PAD[14]; 66 uint32 extmemconfig; 67 uint32 extmemparitycsr; 68 uint32 extmemparityerrdata; 69 uint32 extmemparityerrcnt; 70 uint32 extmemwrctrlandsize; 71 uint32 PAD[84]; 72 uint32 workaround; 73 uint32 pwrctl; /* corerev >= 2 */ 74 uint32 PAD[133]; 75 uint32 sr_control; /* corerev >= 15 */ 76 uint32 sr_status; /* corerev >= 15 */ 77 uint32 sr_address; /* corerev >= 15 */ 78 uint32 sr_data; /* corerev >= 15 */ 79 } sbsocramregs_t; 80 81 #endif /* _LANGUAGE_ASSEMBLY */ 82 83 /* Register offsets */ 84 #define SR_COREINFO 0x00 85 #define SR_BWALLOC 0x04 86 #define SR_BISTSTAT 0x0c 87 #define SR_BANKINDEX 0x10 88 #define SR_BANKSTBYCTL 0x14 89 #define SR_PWRCTL 0x1e8 90 91 /* Coreinfo register */ 92 #define SRCI_PT_MASK 0x00070000 /* corerev >= 6; port type[18:16] */ 93 #define SRCI_PT_SHIFT 16 94 /* port types : SRCI_PT_<processorPT>_<backplanePT> */ 95 #define SRCI_PT_OCP_OCP 0 96 #define SRCI_PT_AXI_OCP 1 97 #define SRCI_PT_ARM7AHB_OCP 2 98 #define SRCI_PT_CM3AHB_OCP 3 99 #define SRCI_PT_AXI_AXI 4 100 #define SRCI_PT_AHB_AXI 5 101 /* corerev >= 3 */ 102 #define SRCI_LSS_MASK 0x00f00000 103 #define SRCI_LSS_SHIFT 20 104 #define SRCI_LRS_MASK 0x0f000000 105 #define SRCI_LRS_SHIFT 24 106 107 /* In corerev 0, the memory size is 2 to the power of the 108 * base plus 16 plus to the contents of the memsize field plus 1. 109 */ 110 #define SRCI_MS0_MASK 0xf 111 #define SR_MS0_BASE 16 112 113 /* 114 * In corerev 1 the bank size is 2 ^ the bank size field plus 14, 115 * the memory size is number of banks times bank size. 116 * The same applies to rom size. 117 */ 118 #define SRCI_ROMNB_MASK 0xf000 119 #define SRCI_ROMNB_SHIFT 12 120 #define SRCI_ROMBSZ_MASK 0xf00 121 #define SRCI_ROMBSZ_SHIFT 8 122 #define SRCI_SRNB_MASK 0xf0 123 #define SRCI_SRNB_SHIFT 4 124 #define SRCI_SRBSZ_MASK 0xf 125 #define SRCI_SRBSZ_SHIFT 0 126 127 #define SRCI_SRNB_MASK_EXT 0x100 128 129 #define SR_BSZ_BASE 14 130 131 /* Standby control register */ 132 #define SRSC_SBYOVR_MASK 0x80000000 133 #define SRSC_SBYOVR_SHIFT 31 134 #define SRSC_SBYOVRVAL_MASK 0x60000000 135 #define SRSC_SBYOVRVAL_SHIFT 29 136 #define SRSC_SBYEN_MASK 0x01000000 /* rev >= 3 */ 137 #define SRSC_SBYEN_SHIFT 24 138 139 /* Power control register */ 140 #define SRPC_PMU_STBYDIS_MASK 0x00000010 /* rev >= 3 */ 141 #define SRPC_PMU_STBYDIS_SHIFT 4 142 #define SRPC_STBYOVRVAL_MASK 0x00000008 143 #define SRPC_STBYOVRVAL_SHIFT 3 144 #define SRPC_STBYOVR_MASK 0x00000007 145 #define SRPC_STBYOVR_SHIFT 0 146 147 /* Extra core capability register */ 148 #define SRECC_NUM_BANKS_MASK 0x000000F0 149 #define SRECC_NUM_BANKS_SHIFT 4 150 #define SRECC_BANKSIZE_MASK 0x0000000F 151 #define SRECC_BANKSIZE_SHIFT 0 152 153 #define SRECC_BANKSIZE(value) (1 << (value)) 154 155 /* CAM bank patch control */ 156 #define SRCBPC_PATCHENABLE 0x80000000 157 158 #define SRP_ADDRESS 0x0001FFFC 159 #define SRP_VALID 0x8000 160 161 /* CAM bank command reg */ 162 #define SRCMD_WRITE 0x00020000 163 #define SRCMD_READ 0x00010000 164 #define SRCMD_DONE 0x80000000 165 166 #define SRCMD_DONE_DLY 1000 167 168 /* bankidx and bankinfo reg defines corerev >= 8 */ 169 #define SOCRAM_BANKINFO_SZMASK 0x7f 170 #define SOCRAM_BANKIDX_ROM_MASK 0x100 171 172 #define SOCRAM_BANKIDX_MEMTYPE_SHIFT 8 173 /* socram bankinfo memtype */ 174 #define SOCRAM_MEMTYPE_RAM 0 175 #define SOCRAM_MEMTYPE_ROM 1 176 #define SOCRAM_MEMTYPE_DEVRAM 2 177 178 #define SOCRAM_BANKINFO_REG 0x40 179 #define SOCRAM_BANKIDX_REG 0x10 180 #define SOCRAM_BANKINFO_STDBY_MASK 0x400 181 #define SOCRAM_BANKINFO_STDBY_TIMER 0x800 182 183 /* bankinfo rev >= 10 */ 184 #define SOCRAM_BANKINFO_DEVRAMSEL_SHIFT 13 185 #define SOCRAM_BANKINFO_DEVRAMSEL_MASK 0x2000 186 #define SOCRAM_BANKINFO_DEVRAMPRO_SHIFT 14 187 #define SOCRAM_BANKINFO_DEVRAMPRO_MASK 0x4000 188 #define SOCRAM_BANKINFO_SLPSUPP_SHIFT 15 189 #define SOCRAM_BANKINFO_SLPSUPP_MASK 0x8000 190 #define SOCRAM_BANKINFO_RETNTRAM_SHIFT 16 191 #define SOCRAM_BANKINFO_RETNTRAM_MASK 0x00010000 192 #define SOCRAM_BANKINFO_PDASZ_SHIFT 17 193 #define SOCRAM_BANKINFO_PDASZ_MASK 0x003E0000 194 #define SOCRAM_BANKINFO_DEVRAMREMAP_SHIFT 24 195 #define SOCRAM_BANKINFO_DEVRAMREMAP_MASK 0x01000000 196 197 /* extracoreinfo register */ 198 #define SOCRAM_DEVRAMBANK_MASK 0xF000 199 #define SOCRAM_DEVRAMBANK_SHIFT 12 200 201 /* bank info to calculate bank size */ 202 #define SOCRAM_BANKINFO_SZBASE 8192 203 #define SOCRAM_BANKSIZE_SHIFT 13 /* SOCRAM_BANKINFO_SZBASE */ 204 205 #endif /* _SBSOCRAM_H */ 206