| /third_party/vixl/test/aarch64/ |
| D | test-utils-aarch64.h | 164 inline T zreg_lane(unsigned code, int lane) const { in zreg_lane()
173 int lane) const { in zreg_lane()
190 int lane) const { in preg_lane()
214 inline bool HasSVELane(T reg, int lane) const { in HasSVELane()
220 inline uint64_t GetSVELane(T reg, int lane) const { in GetSVELane()
414 for (int lane = 0; lane < N; ++lane) { in EqualSVE() local
442 for (int lane = 0; lane < core->GetSVELaneCount(reg.GetLaneSizeInBits()); in EqualSVE() local
467 for (int lane = 0; lane < core->GetSVELaneCount(lane_size); ++lane) { in EqualSVE() local
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| D | test-simulator-aarch64.cc | 1565 for (unsigned lane = 0; lane < vd_lane_count; lane++) { in Test1OpNEON() local
1588 for (unsigned lane = 0; lane < vd_lane_count; lane++) { in Test1OpNEON() local
1608 for (unsigned lane = 0; lane < std::max(vd_lane_count, vn_lane_count); in Test1OpNEON() local
1772 for (unsigned lane = 0; lane < vd_lane_count; lane++) { in Test1OpAcrossNEON() local
1795 for (unsigned lane = 0; lane < vd_lane_count; lane++) { in Test1OpAcrossNEON() local
1806 for (unsigned lane = vd_lane_count; lane < vd_lanes_per_q; lane++) { in Test1OpAcrossNEON() local
1832 for (unsigned lane = 0; lane < vn_lane_count; lane++) { in Test1OpAcrossNEON() local
2033 for (unsigned lane = 0; lane < vd_lane_count; lane++) { in Test2OpNEON() local
2057 for (unsigned lane = 0; lane < vd_lane_count; lane++) { in Test2OpNEON() local
2079 for (unsigned lane = 0; lane < vd_lane_count; lane++) { in Test2OpNEON() local
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| D | test-assembler-aarch64.h | 323 #define ASSERT_EQUAL_SVE_LANE(expected, result, lane) \ argument
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| D | test-utils-aarch64.cc | 360 int lane) { in EqualSVELane()
389 int lane) { in EqualSVELane()
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| /third_party/vixl/src/aarch64/ |
| D | simulator-aarch64.h | 295 void Insert(int lane, T new_value) { in Insert()
309 T GetLane(int lane) const { in GetLane()
349 void ReadLane(T* dst, int lane) const { in ReadLane()
356 void WriteLane(T src, int lane) { in WriteLane()
366 void ReadLane(vixl::internal::SimFloat16* dst, int lane) const { in ReadLane()
372 void WriteLane(vixl::internal::SimFloat16 src, int lane) { in WriteLane()
437 ChunkType GetChunk(int lane) const { return GetActiveMask<ChunkType>(lane); } in GetChunk()
439 void SetChunk(int lane, ChunkType new_value) { in SetChunk()
446 for (int lane = 0; in SetAllBits() local
454 T GetActiveMask(int lane) const { in GetActiveMask()
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| /third_party/optimized-routines/math/ |
| D | v_pow.c | 17 for (int lane = 0; lane < v_lanes64 (); lane++) in V_NAME() local
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| D | v_powf.c | 162 for (int lane = 0; lane < v_lanes32 (); lane++) in V_NAME() local
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| /third_party/typescript/src/debug/ |
| D | dbg.ts | 430 const left = column > 0 ? connectors[column - 1][lane] : 0; constant
431 const above = lane > 0 ? connectors[column][lane - 1] : 0; constant
443 const connector = connectors[column][lane]; constant
445 const node = grid[column][lane]; constant
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| /third_party/mesa3d/src/panfrost/bifrost/ |
| D | bi_lower_divergent_indirects.c | 89 nir_ssa_def *lane = nir_load_subgroup_invocation(b); in bi_lower_divergent_indirects_impl() local
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| /third_party/node/deps/base64/base64/lib/arch/neon32/ |
| D | dec_loop.c | 25 dec_loop_neon32_lane (uint8x16_t *lane) in dec_loop_neon32_lane()
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| D | macro-assembler-arm64.h | 1209 void St1(const VRegister& vt, int lane, const MemOperand& dst) { in St1()
1650 void Ld1(const VRegister& vt, int lane, const MemOperand& src) { in Ld1()
1662 void Ld2(const VRegister& vt, const VRegister& vt2, int lane, in Ld2()
1677 int lane, const MemOperand& src) { in Ld3()
1692 const VRegister& vt4, int lane, const MemOperand& src) { in Ld4()
1715 void St2(const VRegister& vt, const VRegister& vt2, int lane, in St2()
1721 int lane, const MemOperand& dst) { in St3()
1726 const VRegister& vt4, int lane, const MemOperand& dst) { in St4()
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| /third_party/astc-encoder/Source/ |
| D | astcenc_vecmathlib_none_4.h | 105 template <int l> ASTCENC_SIMD_INLINE float lane() const in lane() function
249 template <int l> ASTCENC_SIMD_INLINE int lane() const in lane() function
357 template <int l> ASTCENC_SIMD_INLINE float lane() const in lane() function
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| D | astcenc_vecmathlib_neon_4.h | 100 template <int l> ASTCENC_SIMD_INLINE float lane() const in lane() function
244 template <int l> ASTCENC_SIMD_INLINE int lane() const in lane() function
362 template <int32_t l> ASTCENC_SIMD_INLINE bool lane() const in lane() function
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| D | astcenc_vecmathlib_sse_4.h | 100 template <int l> ASTCENC_SIMD_INLINE float lane() const in lane() function
260 template <int l> ASTCENC_SIMD_INLINE int lane() const in lane() function
382 template <int l> ASTCENC_SIMD_INLINE bool lane() const in lane() function
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| D | astcenc_vecmathlib_avx2_8.h | 100 template <int l> ASTCENC_SIMD_INLINE float lane() const in lane() function
216 template <int l> ASTCENC_SIMD_INLINE int lane() const in lane() function
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| /third_party/vixl/src/aarch32/ |
| D | instructions-aarch32.h | 224 SRegister GetLane(uint32_t lane) const { in GetLane()
327 DRegisterLane(DRegister reg, uint32_t lane) in DRegisterLane()
329 DRegisterLane(uint32_t code, uint32_t lane) : DRegister(code), lane_(lane) {} in DRegisterLane()
345 int* lane) { in ExtractDRegisterAndLane()
369 DRegister GetDLane(uint32_t lane) const { in GetDLane()
376 SRegister GetSLane(uint32_t lane) const { in GetSLane()
712 NeonRegisterList(DRegister reg, int lane) in NeonRegisterList()
737 int lane) in NeonRegisterList()
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| D | disasm-aarch32.cc | 76 DecodeNeon(int lane, SpacingType spacing) in DecodeNeon()
330 DataTypeValue Dt_U_opc1_opc2_1_Decode(uint32_t value, unsigned* lane) { in Dt_U_opc1_opc2_1_Decode()
355 DataTypeValue Dt_opc1_opc2_1_Decode(uint32_t value, unsigned* lane) { in Dt_opc1_opc2_1_Decode()
372 DataTypeValue Dt_imm4_1_Decode(uint32_t value, unsigned* lane) { in Dt_imm4_1_Decode()
840 int lane = (value >> 1) & 0x7; in Index_1_Decode() local
846 int lane = (value >> 2) & 0x3; in Index_1_Decode() local
852 int lane = (value >> 3) & 0x1; in Index_1_Decode() local
872 int lane = (value >> 1) & 0x7; in Align_index_align_1_Decode() local
885 int lane = (value >> 2) & 0x3; in Align_index_align_1_Decode() local
898 int lane = (value >> 3) & 0x1; in Align_index_align_1_Decode() local
[all …]
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| /third_party/mesa3d/src/nouveau/codegen/ |
| D | nv50_ir_lowering_gm107.cpp | 141 Value *lane = bld.mkImm(l); in handleManualTXD() local
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| /third_party/node/deps/v8/src/codegen/arm/ |
| D | macro-assembler-arm.cc | 1087 NeonDataType dt, int lane) { in CallRecordWriteStub()
1099 NeonDataType dt, int lane) { in CallRecordWriteStub()
1108 int lane) { in CallRecordWriteStub()
1114 int lane) { in CallRecordWriteStub()
1120 Register src_lane, NeonDataType dt, int lane) { in CallRecordWriteStub()
1133 SwVfpRegister src_lane, int lane) { in CallRecordWriteStub()
1140 DwVfpRegister src_lane, int lane) { in CallRecordWriteStub()
1147 uint8_t lane, NeonMemOperand src) { in CallRecordWriteStub()
1157 uint8_t lane, NeonMemOperand dst) { in CallRecordWriteStub()
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| /third_party/skia/third_party/externals/swiftshader/src/Pipeline/ |
| D | SpirvShaderDebugger.cpp | 266 for(int lane = 0; lane < sw::SIMD::Width; lane++) in get() local
1182 int const lane; member
2018 int lane) in LocalVariableValue()
2171 for(size_t lane = 0; lane < sw::SIMD::Width; lane++) in Data() local
2333 for(size_t lane = 0; lane < sw::SIMD::Width; lane++) in updateFrameLocals() local
2345 for(int lane = 0; lane < sw::SIMD::Width; lane++) in getOrCreateLocals() local
2379 for(int lane = 0; lane < sw::SIMD::Width; lane++) in getOrCreateLocals() local
2386 for(int lane = 0; lane < sw::SIMD::Width; lane++) in getOrCreateLocals() local
2404 for(int lane = 0; lane < sw::SIMD::Width; lane++) in buildGlobal() local
2415 for(int lane = 0; lane < sw::SIMD::Width; lane++) in buildGlobals() local
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| /third_party/mesa3d/src/panfrost/bifrost/valhall/ |
| D | valhall.h | 79 bool lane : 1; member
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| D | valhall.py | 103 …halfswizzle = False, widen = False, lanes = False, combine = False, lane = None, absneg = False, n… argument
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| /third_party/node/deps/v8/src/codegen/shared-ia32-x64/ |
| D | macro-assembler-shared-ia32-x64.cc | 133 uint8_t lane) { in F64x2ExtractLane()
152 DoubleRegister rep, uint8_t lane) { in F64x2ReplaceLane()
333 uint8_t lane) { in F32x4ExtractLane()
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| /third_party/mbedtls/library/ |
| D | sha3.c | 103 uint64_t lane[5]; in keccak_f1600() local
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| /third_party/node/deps/v8/src/compiler/ |
| D | int64-lowering.cc | 1040 int32_t lane = OpParameter<int32_t>(node->op()); in LowerNode() local
1048 int32_t lane = OpParameter<int32_t>(node->op()); in LowerNode() local
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