Searched defs:pp_smu_funcs_nv (Results 1 – 2 of 2) sorted by relevance
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/ |
| D | dm_pp_smu.h | 167 struct pp_smu_funcs_nv { struct
168 struct pp_smu pp_smu;
173 enum pp_smu_status (*set_display_count)(struct pp_smu *pp, int count);
178 enum pp_smu_status (*set_hard_min_dcfclk_by_freq)(struct pp_smu *pp, int Mhz);
184 enum pp_smu_status (*set_min_deep_sleep_dcfclk)(struct pp_smu *pp, int Mhz);
189 enum pp_smu_status (*set_hard_min_uclk_by_freq)(struct pp_smu *pp, int Mhz);
194 enum pp_smu_status (*set_hard_min_socclk_by_freq)(struct pp_smu *pp, int Mhz);
197 enum pp_smu_status (*set_pme_wa_enable)(struct pp_smu *pp);
202 enum pp_smu_status (*set_voltage_by_freq)(struct pp_smu *pp,
217 enum pp_smu_status (*set_wm_ranges)(struct pp_smu *pp,
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/ |
| D | dm_pp_smu.h | 167 struct pp_smu_funcs_nv { struct
168 struct pp_smu pp_smu;
173 enum pp_smu_status (*set_display_count)(struct pp_smu *pp, int count);
178 enum pp_smu_status (*set_hard_min_dcfclk_by_freq)(struct pp_smu *pp, int Mhz);
184 enum pp_smu_status (*set_min_deep_sleep_dcfclk)(struct pp_smu *pp, int Mhz);
189 enum pp_smu_status (*set_hard_min_uclk_by_freq)(struct pp_smu *pp, int Mhz);
194 enum pp_smu_status (*set_hard_min_socclk_by_freq)(struct pp_smu *pp, int Mhz);
197 enum pp_smu_status (*set_pme_wa_enable)(struct pp_smu *pp);
202 enum pp_smu_status (*set_voltage_by_freq)(struct pp_smu *pp,
217 enum pp_smu_status (*set_wm_ranges)(struct pp_smu *pp,
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