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Searched defs:uaddlp (Results 1 – 5 of 5) sorted by relevance

/third_party/vixl/test/aarch64/
Dtest-trace-aarch64.cc2209 __ uaddlp(v7.V1D(), v9.V2S()); in GenerateTestSequenceNEON() local
2210 __ uaddlp(v26.V2D(), v4.V4S()); in GenerateTestSequenceNEON() local
2211 __ uaddlp(v28.V2S(), v1.V4H()); in GenerateTestSequenceNEON() local
2212 __ uaddlp(v20.V4H(), v31.V8B()); in GenerateTestSequenceNEON() local
2213 __ uaddlp(v16.V4S(), v17.V8H()); in GenerateTestSequenceNEON() local
2214 __ uaddlp(v6.V8H(), v2.V16B()); in GenerateTestSequenceNEON() local
/third_party/node/deps/v8/src/codegen/arm64/
Dassembler-arm64.cc2001 void Assembler::uaddlp(const VRegister& vd, const VRegister& vn) { in uaddlp() function in v8::internal::Assembler
/third_party/vixl/src/aarch64/
Dassembler-aarch64.cc4767 void Assembler::uaddlp(const VRegister& vd, const VRegister& vn) { in uaddlp() function in vixl::aarch64::Assembler
Dlogic-aarch64.cc2452 LogicVRegister Simulator::uaddlp(VectorFormat vform, in uaddlp() function in vixl::aarch64::Simulator
/third_party/node/deps/v8/src/execution/arm64/
Dsimulator-logic-arm64.cc1961 LogicVRegister Simulator::uaddlp(VectorFormat vform, LogicVRegister dst, in uaddlp() function in v8::internal::Simulator