Searched defs:uaddlv (Results 1 – 5 of 5) sorted by relevance
| /third_party/vixl/test/aarch64/ |
| D | test-trace-aarch64.cc | 2215 __ uaddlv(d28, v22.V4S()); in GenerateTestSequenceNEON() local
2216 __ uaddlv(h0, v19.V16B()); in GenerateTestSequenceNEON() local
2217 __ uaddlv(h30, v30.V8B()); in GenerateTestSequenceNEON() local
2218 __ uaddlv(s24, v18.V4H()); in GenerateTestSequenceNEON() local
2219 __ uaddlv(s10, v0.V8H()); in GenerateTestSequenceNEON() local
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| D | assembler-arm64.cc | 2025 void Assembler::uaddlv(const VRegister& vd, const VRegister& vn) { in uaddlv() function in v8::internal::Assembler
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| /third_party/vixl/src/aarch64/ |
| D | assembler-aarch64.cc | 4801 void Assembler::uaddlv(const VRegister& vd, const VRegister& vn) { in uaddlv() function in vixl::aarch64::Assembler
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| D | logic-aarch64.cc | 1269 LogicVRegister Simulator::uaddlv(VectorFormat vform, in uaddlv() function in vixl::aarch64::Simulator
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| /third_party/node/deps/v8/src/execution/arm64/ |
| D | simulator-logic-arm64.cc | 1201 LogicVRegister Simulator::uaddlv(VectorFormat vform, LogicVRegister dst, in uaddlv() function in v8::internal::Simulator
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