| /third_party/ffmpeg/libavcodec/arm/ |
| D | sbrdsp_neon.S | 95 vswp d0, d1 define
111 vswp d0, d1 define
114 vswp d4, d5 define
131 vswp d2, d3 define
139 vswp d6, d7 define
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| D | vc1dsp_neon.S | 145 vswp d4, d5 @ q2 = src[48]|src[16] define
162 vswp d2, d3 @ q1 = src[40]|src[8] define
164 vswp d6, d7 @ q3 = src[56]|src[24] define
167 vswp d3, d6 @ q1 = src[40]|src[56], q3 = src[8]|src[24] define
172 vswp d6, d7 @ q3 = src[24]|src[8] define
173 vswp d2, d3 @ q1 = src[56]|src[40] define
604 …vswp d1, d2 @ so that we can later access column 1 and column 3 as a single q1… define
630 …vswp d2, d3 @ so that we can later access column 1 and column 3 in order as a … define
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| D | rv34dsp_neon.S | 47 vswp d3, d6 define
48 vswp d5, d16 define
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| D | rv40dsp_neon.S | 293 vswp d0, d1 define
392 vswp d0, d1 define
531 vswp d0, d1 define
629 vswp d0, d1 define
842 vswp d3, d6 @ q1q2, p1p0 define
912 vswp d4, d5 define
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| D | sbcdsp_neon.S | 547 vswp d5, d20 define
566 vswp d5, d20 define
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| D | fft_neon.S | 152 vswp d1, d26 @ q0{t1,t2,t3,t4} q13{t6,t5,t7,t8} define
153 vswp d3, d30 @ q1{t1a,t2a,t3a,t4a} q15{t6a,t5a,t7a,t8a} define
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| D | h264idct_neon.S | 28 vswp d1, d2 define
46 vswp d1, d3 define
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| D | hevcdsp_idct_neon.S | 491 vswp d0, d8 define
493 vswp d0, d8 define
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| D | hpeldsp_neon.S | 231 vswp d1, d2 define
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| D | vp9itxfm_16bpp_neon.S | 414 vswp d5, d16 define
415 vswp d7, d18 define
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| /third_party/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 6076 void vswp(DataType dt, DRegister rd, DRegister rm) { vswp(al, dt, rd, rm); } in vswp() function
6077 void vswp(DRegister rd, DRegister rm) { in vswp() function
6080 void vswp(Condition cond, DRegister rd, DRegister rm) { in vswp() function
6085 void vswp(DataType dt, QRegister rd, QRegister rm) { vswp(al, dt, rd, rm); } in vswp() function
6086 void vswp(QRegister rd, QRegister rm) { in vswp() function
6089 void vswp(Condition cond, QRegister rd, QRegister rm) { in vswp() function
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| D | assembler-aarch32.cc | 27569 void Assembler::vswp(Condition cond, DataType dt, DRegister rd, DRegister rm) { in vswp() function in vixl::aarch32::Assembler
27590 void Assembler::vswp(Condition cond, DataType dt, QRegister rd, QRegister rm) { in vswp() function in vixl::aarch32::Assembler
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| D | disasm-aarch32.cc | 6855 void Disassembler::vswp(Condition cond, in vswp() function in vixl::aarch32::Disassembler
6864 void Disassembler::vswp(Condition cond, in vswp() function in vixl::aarch32::Disassembler
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| /third_party/node/deps/v8/src/codegen/arm/ |
| D | assembler-arm.cc | 4175 void Assembler::vswp(DwVfpRegister dst, DwVfpRegister src) { in vswp() function in v8::internal::Assembler
4183 void Assembler::vswp(QwNeonRegister dst, QwNeonRegister src) { in vswp() function in v8::internal::Assembler
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