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/kernel/linux/linux-5.10/drivers/dma/
Dxgene-dma.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Applied Micro X-Gene SoC DMA engine Driver
15 #include <linux/dma-mapping.h>
26 /* X-Gene DMA ring csr registers and bit definations */
43 ((m) = ((m) & ~BIT(31 - (v))) | BIT(31 - (v)))
45 ((m) &= (~BIT(31 - (v))))
76 /* X-Gene DMA device csr registers and bit definitions */
105 /* X-Gene SoC EFUSE csr register and bit defination */
109 /* X-Gene DMA Descriptor format */
126 /* X-Gene DMA descriptor empty s/w signature */
[all …]
/kernel/linux/linux-6.6/drivers/dma/
Dxgene-dma.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Applied Micro X-Gene SoC DMA engine Driver
15 #include <linux/dma-mapping.h>
27 /* X-Gene DMA ring csr registers and bit definations */
44 ((m) = ((m) & ~BIT(31 - (v))) | BIT(31 - (v)))
46 ((m) &= (~BIT(31 - (v))))
77 /* X-Gene DMA device csr registers and bit definitions */
106 /* X-Gene SoC EFUSE csr register and bit defination */
110 /* X-Gene DMA Descriptor format */
127 /* X-Gene DMA descriptor empty s/w signature */
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/kernel/linux/linux-6.6/drivers/dma/sf-pdma/
Dsf-pdma.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * - drivers/dma/fsl-edma.c
8 * - drivers/dma/dw-edma/
9 * - drivers/dma/pxa-dma.c
12 * - Chapter 12 "Platform DMA Engine (PDMA)" of
13 * SiFive FU540-C000 v1.0
14 * https://static.dev.sifive.com/FU540-C000-v1.0.pdf
21 #include <linux/dma-mapping.h>
25 #include "sf-pdma.h"
60 desc->chan = chan; in sf_pdma_alloc_desc()
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Dsf-pdma.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
7 * - drivers/dma/fsl-edma.c
8 * - drivers/dma/dw-edma/
9 * - drivers/dma/pxa-dma.c
12 * - Chapter 12 "Platform DMA Engine (PDMA)" of
13 * SiFive FU540-C000 v1.0
14 * https://static.dev.sifive.com/FU540-C000-v1.0.pdf
20 #include <linux/dma-direction.h>
23 #include "../virt-dma.h"
36 #define PDMA_ACT_TYPE 0x104 /* Read-only */
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/kernel/linux/linux-5.10/drivers/dma/sf-pdma/
Dsf-pdma.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * - drivers/dma/fsl-edma.c
8 * - drivers/dma/dw-edma/
9 * - drivers/dma/pxa-dma.c
12 * - Chapter 12 "Platform DMA Engine (PDMA)" of
13 * SiFive FU540-C000 v1.0
14 * https://static.dev.sifive.com/FU540-C000-v1.0.pdf
21 #include <linux/dma-mapping.h>
25 #include "sf-pdma.h"
60 desc->chan = chan; in sf_pdma_alloc_desc()
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Dsf-pdma.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
7 * - drivers/dma/fsl-edma.c
8 * - drivers/dma/dw-edma/
9 * - drivers/dma/pxa-dma.c
12 * - Chapter 12 "Platform DMA Engine (PDMA)" of
13 * SiFive FU540-C000 v1.0
14 * https://static.dev.sifive.com/FU540-C000-v1.0.pdf
20 #include <linux/dma-direction.h>
23 #include "../virt-dma.h"
40 #define PDMA_ACT_TYPE 0x104 /* Read-only */
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/dma/
Dsifive,fu540-c000-pdma.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/dma/sifive,fu540-c000-pdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Green Wan <green.wan@sifive.com>
11 - Palmer Debbelt <palmer@sifive.com>
12 - Paul Walmsley <paul.walmsley@sifive.com>
23 https://static.dev.sifive.com/FU540-C000-v1.0.pdf
26 - $ref: dma-controller.yaml#
31 - enum:
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Dmmp-dma.txt7 - compatible: Should be "marvell,pdma-1.0"
8 - reg: Should contain DMA registers location and length.
9 - interrupts: Either contain all of the per-channel DMA interrupts
10 or one irq for pdma device
13 - dma-channels: Number of DMA channels supported by the controller (defaults
15 - #dma-channels: deprecated
16 - dma-requests: Number of DMA requestor lines supported by the controller
18 - #dma-requests: deprecated
20 "marvell,pdma-1.0"
29 * Using this method, interrupt-parent is required as demuxer
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/dma/
Dmmp-dma.txt7 - compatible: Should be "marvell,pdma-1.0"
8 - reg: Should contain DMA registers location and length.
9 - interrupts: Either contain all of the per-channel DMA interrupts
10 or one irq for pdma device
13 - #dma-channels: Number of DMA channels supported by the controller (defaults
15 - #dma-requests: Number of DMA requestor lines supported by the controller
18 "marvell,pdma-1.0"
27 * Using this method, interrupt-parent is required as demuxer
28 * For example, pxa688 icu register 0x128, bit 0~15 is PDMA channel irq,
31 pdma: dma-controller@d4000000 {
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Dsifive,fu540-c000-pdma.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/dma/sifive,fu540-c000-pdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Green Wan <green.wan@sifive.com>
11 - Palmer Debbelt <palmer@sifive.com>
12 - Paul Walmsley <paul.walmsley@sifive.com>
23 https://static.dev.sifive.com/FU540-C000-v1.0.pdf
28 - const: sifive,fu540-c000-pdma
37 '#dma-cells':
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/kernel/linux/linux-5.10/include/linux/dma/
Dk3-psil.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com
16 * enum udma_tp_level - Channel Throughput Levels
29 * enum psil_endpoint_type - PSI-L Endpoint type
31 * @PSIL_EP_PDMA_XY: XY mode PDMA
32 * @PSIL_EP_PDMA_MCAN: MCAN mode PDMA
33 * @PSIL_EP_PDMA_AASRC: AASRC mode PDMA
43 * struct psil_endpoint_config - PSI-L Endpoint configuration
44 * @ep_type: PSI-L endpoint type
51 * @pdma_acc32: ACC32 must be enabled on the PDMA side
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/kernel/linux/linux-6.6/include/linux/dma/
Dk3-psil.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com
16 * enum udma_tp_level - Channel Throughput Levels
29 * enum psil_endpoint_type - PSI-L Endpoint type
31 * @PSIL_EP_PDMA_XY: XY mode PDMA
32 * @PSIL_EP_PDMA_MCAN: MCAN mode PDMA
33 * @PSIL_EP_PDMA_AASRC: AASRC mode PDMA
43 * struct psil_endpoint_config - PSI-L Endpoint configuration
44 * @ep_type: PSI-L endpoint type
50 * @pdma_acc32: ACC32 must be enabled on the PDMA side
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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/crypto/
Dartpec6-crypto.txt1 Axis crypto engine with PDMA interface.
4 - compatible : Should be one of the following strings:
5 "axis,artpec6-crypto" for the version in the Axis ARTPEC-6 SoC
6 "axis,artpec7-crypto" for the version in the Axis ARTPEC-7 SoC.
7 - reg: Base address and size for the PDMA register area.
8 - interrupts: Interrupt handle for the PDMA interrupt line.
13 compatible = "axis,artpec6-crypto";
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/crypto/
Dartpec6-crypto.txt1 Axis crypto engine with PDMA interface.
4 - compatible : Should be one of the following strings:
5 "axis,artpec6-crypto" for the version in the Axis ARTPEC-6 SoC
6 "axis,artpec7-crypto" for the version in the Axis ARTPEC-7 SoC.
7 - reg: Base address and size for the PDMA register area.
8 - interrupts: Interrupt handle for the PDMA interrupt line.
13 compatible = "axis,artpec6-crypto";
/kernel/linux/linux-5.10/drivers/net/ethernet/mediatek/
Dmtk_eth_soc.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
12 #include <linux/dma-mapping.h>
44 #define NEXT_DESP_IDX(X, Y) (((X) + 1) & ((Y) - 1))
69 /* PDMA HW LRO Alter Flow Timer Register */
90 /* Unicast Filter MAC Address Register - Low */
93 /* Unicast Filter MAC Address Register - High */
96 /* PDMA RX Base Pointer Register */
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/kernel/linux/linux-6.6/arch/mips/boot/dts/ingenic/
Dx1830.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/ingenic,tcu.h>
3 #include <dt-bindings/clock/ingenic,x1830-cgu.h>
4 #include <dt-bindings/dma/x1830-dma.h>
7 #address-cells = <1>;
8 #size-cells = <1>;
12 #address-cells = <1>;
13 #size-cells = <0>;
17 compatible = "ingenic,xburst-fpu2.0-mxu2.0";
21 clock-names = "cpu";
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Dx1000.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/ingenic,tcu.h>
3 #include <dt-bindings/clock/ingenic,x1000-cgu.h>
4 #include <dt-bindings/dma/x1000-dma.h>
7 #address-cells = <1>;
8 #size-cells = <1>;
12 #address-cells = <1>;
13 #size-cells = <0>;
17 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
21 clock-names = "cpu";
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/kernel/linux/linux-6.6/arch/arm/boot/dts/intel/pxa/
Dpxa3xx.dtsi1 // SPDX-License-Identifier: GPL-2.0
7 (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \
8 (gpio <= 98) ? (0x0400 + 4 * (gpio - 27)) : \
9 (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \
18 (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \
19 (gpio <= 29) ? (0x0400 + 4 * (gpio - 27)) : \
20 (gpio <= 98) ? (0x0418 + 4 * (gpio - 30)) : \
21 (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \
23 (gpio <= 268) ? (0x052c + 4 * (gpio - 263)) : \
33 (gpio <= 9) ? (0x028c + 4 * (gpio - 5)) : \
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Dpxa27x.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include "dt-bindings/clock/pxa-clock.h"
11 pdma: dma-controller@40000000 { label
12 compatible = "marvell,pdma-1.0";
15 #dma-cells = <2>;
17 #dma-channels = <32>;
18 dma-channels = <32>;
19 #dma-requests = <75>;
20 dma-requests = <75>;
24 pxairq: interrupt-controller@40d00000 {
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/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dpxa3xx.dtsi1 // SPDX-License-Identifier: GPL-2.0
7 (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \
8 (gpio <= 98) ? (0x0400 + 4 * (gpio - 27)) : \
9 (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \
18 (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \
19 (gpio <= 29) ? (0x0400 + 4 * (gpio - 27)) : \
20 (gpio <= 98) ? (0x0418 + 4 * (gpio - 30)) : \
21 (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \
23 (gpio <= 268) ? (0x052c + 4 * (gpio - 263)) : \
33 (gpio <= 9) ? (0x028c + 4 * (gpio - 5)) : \
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Dpxa27x.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include "dt-bindings/clock/pxa-clock.h"
11 pdma: dma-controller@40000000 { label
12 compatible = "marvell,pdma-1.0";
15 #dma-channels = <32>;
16 #dma-cells = <2>;
17 #dma-requests = <75>;
21 pxairq: interrupt-controller@40d00000 {
22 marvell,intc-priority;
23 marvell,intc-nr-irqs = <34>;
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/kernel/linux/linux-5.10/drivers/video/fbdev/riva/
Dnvreg.h3 * Copyright 1996-1997 David J. McKay
30 #define BITMASK(t,b) (((unsigned)(1U << (((t)-(b)+1)))-1) << (b))
41 #define DEVICE_SIZE(device) ((1?NV##_##device) - DEVICE_BASE(device)+1)
84 #define PDMA_Write(reg,value) DEVICE_WRITE(PDMA,reg,value)
85 #define PDMA_Read(reg) DEVICE_READ(PDMA,reg)
86 #define PDMA_Print(reg) DEVICE_PRINT(PDMA,reg)
87 #define PDMA_Def(mask,value) DEVICE_DEF(PDMA,mask,value)
88 #define PDMA_Val(mask,value) DEVICE_VALUE(PDMA,mask,value)
89 #define PDMA_Mask(mask) DEVICE_MASK(PDMA,mask)
/kernel/linux/linux-6.6/drivers/video/fbdev/riva/
Dnvreg.h3 * Copyright 1996-1997 David J. McKay
30 #define BITMASK(t,b) (((unsigned)(1U << (((t)-(b)+1)))-1) << (b))
41 #define DEVICE_SIZE(device) ((1?NV##_##device) - DEVICE_BASE(device)+1)
84 #define PDMA_Write(reg,value) DEVICE_WRITE(PDMA,reg,value)
85 #define PDMA_Read(reg) DEVICE_READ(PDMA,reg)
86 #define PDMA_Print(reg) DEVICE_PRINT(PDMA,reg)
87 #define PDMA_Def(mask,value) DEVICE_DEF(PDMA,mask,value)
88 #define PDMA_Val(mask,value) DEVICE_VALUE(PDMA,mask,value)
89 #define PDMA_Mask(mask) DEVICE_MASK(PDMA,mask)
/kernel/linux/linux-5.10/arch/mips/boot/dts/ingenic/
Dx1830.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/ingenic,tcu.h>
3 #include <dt-bindings/clock/x1830-cgu.h>
4 #include <dt-bindings/dma/x1830-dma.h>
7 #address-cells = <1>;
8 #size-cells = <1>;
12 #address-cells = <1>;
13 #size-cells = <0>;
17 compatible = "ingenic,xburst-fpu2.0-mxu2.0";
21 clock-names = "cpu";
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Dx1000.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/ingenic,tcu.h>
3 #include <dt-bindings/clock/x1000-cgu.h>
4 #include <dt-bindings/dma/x1000-dma.h>
7 #address-cells = <1>;
8 #size-cells = <1>;
12 #address-cells = <1>;
13 #size-cells = <0>;
17 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
21 clock-names = "cpu";
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