| /kernel/linux/linux-6.6/arch/arm64/kvm/hyp/ |
| D | exception.c | 75 * This performs the exception entry at a given EL (@target_mode), stashing PC
77 * The EL passed to this function *must* be a non-secure, privileged mode with
85 * For the SPSR_ELx layout for AArch64, see ARM DDI 0487E.a page C5-429.
86 * For the SPSR_ELx layout for AArch32, see ARM DDI 0487E.a page C5-426.
140 // See ARM DDI 0487E.a, page D5-2579. in enter_exception64()
144 // See ARM DDI 0487E.a, page D5-2578. in enter_exception64()
150 // See ARM DDI 0487E.a, page D2-2452. in enter_exception64()
153 // See ARM DDI 0487E.a, page D1-2306. in enter_exception64()
156 // See ARM DDI 0487E.a, page D13-3258 in enter_exception64()
161 // See ARM DDI 0487E.a, pages D1-2293 to D1-2294. in enter_exception64()
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| /kernel/linux/linux-5.10/arch/arm64/kvm/ |
| D | aarch32.c | 66 * - ARM DDI 0487E.a, page G8-6264
69 * - ARM DDI 0487E.a, page C5-426
89 // See ARM DDI 0487E.a, section G1.12.3 in get_except32_cpsr()
95 // See ARM DDI 0487E.a, page G8-6244 in get_except32_cpsr()
101 // See ARM DDI 0487E.a, page G8-6246 in get_except32_cpsr()
109 // See ARM DDI 0487E.a, page G1-5527 in get_except32_cpsr()
117 // See ARM DDI 0487E.a, page G8-6245 in get_except32_cpsr()
122 // CPSR.A is unchanged upon an exception to Undefined, Supervisor in get_except32_cpsr()
123 // CPSR.A is set upon an exception to other modes in get_except32_cpsr()
124 // See ARM DDI 0487E.a, pages G1-5515 to G1-5516 in get_except32_cpsr()
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| D | inject_fault.c | 30 * This performs the exception entry at a given EL (@target_mode), stashing PC
32 * The EL passed to this function *must* be a non-secure, privileged mode with
40 * For the SPSR_ELx layout for AArch64, see ARM DDI 0487E.a page C5-429.
41 * For the SPSR_ELx layout for AArch32, see ARM DDI 0487E.a page C5-426.
89 // See ARM DDI 0487E.a, page D5-2579. in enter_exception64()
93 // See ARM DDI 0487E.a, page D5-2578. in enter_exception64()
99 // See ARM DDI 0487E.a, page D2-2452. in enter_exception64()
102 // See ARM DDI 0487E.a, page D1-2306. in enter_exception64()
105 // See ARM DDI 0487E.a, page D13-3258 in enter_exception64()
110 // See ARM DDI 0487E.a, pages D1-2293 to D1-2294. in enter_exception64()
[all …]
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| /kernel/linux/linux-5.10/Documentation/trace/coresight/ |
| D | coresight-cpu-debug.rst | 11 Coresight CPU debug module is defined in ARMv8-a architecture reference manual
12 (ARM DDI 0487A.k) Chapter 'Part H: External debug', the CPU can integrate
43 - The driver supports a CPU running in either AArch64 or AArch32 mode. The
44 registers naming convention is a bit different between them, AArch64 uses
45 'ED' for register prefix (ARM DDI 0487A.k, chapter H9.1) and AArch32 uses
46 'DBG' as prefix (ARM DDI 0487A.k, chapter G5.1). The driver is unified to
49 - ARMv8-a (ARM DDI 0487A.k) and ARMv7-a (ARM DDI 0406C.b) have different
52 If PCSROffset=0b0000, on ARMv8-a the feature of EDPCSR is not implemented;
53 but ARMv7-a defines "PCSR samples are offset by a value that depends on the
54 instruction set state". For ARMv7-a, the driver checks furthermore if CPU
[all …]
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| /kernel/linux/linux-6.6/Documentation/trace/coresight/ |
| D | coresight-cpu-debug.rst | 11 Coresight CPU debug module is defined in ARMv8-a architecture reference manual
12 (ARM DDI 0487A.k) Chapter 'Part H: External debug', the CPU can integrate
43 - The driver supports a CPU running in either AArch64 or AArch32 mode. The
44 registers naming convention is a bit different between them, AArch64 uses
45 'ED' for register prefix (ARM DDI 0487A.k, chapter H9.1) and AArch32 uses
46 'DBG' as prefix (ARM DDI 0487A.k, chapter G5.1). The driver is unified to
49 - ARMv8-a (ARM DDI 0487A.k) and ARMv7-a (ARM DDI 0406C.b) have different
52 If PCSROffset=0b0000, on ARMv8-a the feature of EDPCSR is not implemented;
53 but ARMv7-a defines "PCSR samples are offset by a value that depends on the
54 instruction set state". For ARMv7-a, the driver checks furthermore if CPU
[all …]
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| /kernel/linux/linux-5.10/arch/arm64/kernel/ |
| D | cpuinfo.c | 163 * Dump out the common processor features in a single line. in c_show()
165 * rather than attempting to parse this, but there's a body of in c_show()
234 * The ARM ARM uses the phrase "32-bit register" to describe a register
235 * whose upper 32 bits are RES0 (per C5.1.1, ARM DDI 0487A.i), however
237 * be made use of in future, and between ARM DDI 0487A.c and ARM DDI
238 * 0487A.d CLIDR_EL1 was expanded from 32-bit to 64-bit.
357 * when there is a mismatch across the CPUs. Keep track of the in __cpuinfo_store_cpu()
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| D | hibernate-asm.S | 20 * in the tlb, switch the ttbr to a zero page when we invalidate the old
21 * records. D4.7.1 'General TLB maintenance requirements' in ARM DDI 0487A.i
22 * Even switching to our copied tables will cause a changed output address at
45 * Because this code has to be copied to a 'safe' page, it can't call out to
51 * switches to a copy of the linear map in ttbr1, performs the restore, then
65 * x5: physical address of a zero page that remains zero after resume
71 * with a break-before-make via the zero page
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| /kernel/linux/linux-6.6/Documentation/arch/arm64/ |
| D | hugetlbpage.rst | 18 These are regular hugepages where a pmd or a pud page table entry points to a
26 The architecture provides a contiguous bit in the translation table entries
27 (D4.5.3, ARM DDI 0487C.a) that hints to the MMU to indicate that it is one of a
28 contiguous set of entries that can be cached in a single TLB entry.
|
| /kernel/linux/linux-5.10/Documentation/arm64/ |
| D | hugetlbpage.rst | 18 These are regular hugepages where a pmd or a pud page table entry points to a
26 The architecture provides a contiguous bit in the translation table entries
27 (D4.5.3, ARM DDI 0487C.a) that hints to the MMU to indicate that it is one of a
28 contiguous set of entries that can be cached in a single TLB entry.
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| /kernel/linux/linux-5.10/Documentation/translations/zh_CN/arm64/ |
| D | hugetlbpage.rst | 29 架构中转换页表条目(D4.5.3, ARM DDI 0487C.a)中提供一个连续
|
| /kernel/linux/linux-6.6/Documentation/translations/zh_TW/arch/arm64/ |
| D | hugetlbpage.rst | 32 架構中轉換頁表條目(D4.5.3, ARM DDI 0487C.a)中提供一個連續
|
| /kernel/linux/linux-6.6/Documentation/translations/zh_CN/arch/arm64/ |
| D | hugetlbpage.rst | 29 架构中转换页表条目(D4.5.3, ARM DDI 0487C.a)中提供一个连续
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/ |
| D | coresight-cpu-debug.txt | 4 reference manual (ARM DDI 0487A.k) Chapter 'Part H: External debug'. The
34 - power-domains: a phandle to the debug power domain. We use "power-domains"
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/arm/ |
| D | arm,coresight-cpu-debug.yaml | 17 reference manual (ARM DDI 0487A.k) Chapter 'Part H: External debug'. The
53 A phandle to the cpu this debug component is bound to.
59 A phandle to the debug power domain if the debug logic has its own
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| /kernel/linux/linux-6.6/arch/arm64/kernel/ |
| D | cpuinfo.c | 201 * Dump out the common processor features in a single line. in c_show()
203 * rather than attempting to parse this, but there's a body of in c_show()
272 * The ARM ARM uses the phrase "32-bit register" to describe a register
273 * whose upper 32 bits are RES0 (per C5.1.1, ARM DDI 0487A.i), however
275 * be made use of in future, and between ARM DDI 0487A.c and ARM DDI
276 * 0487A.d CLIDR_EL1 was expanded from 32-bit to 64-bit.
434 * when there is a mismatch across the CPUs. Keep track of the in __cpuinfo_store_cpu()
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| /kernel/linux/linux-5.10/arch/arm64/include/asm/ |
| D | daifflags.h | 34 /* Don't really care for a dsb here, we don't intend to enable IRQs */ in local_daif_mask()
98 * From the ARM ARM DDI 0487D.a, section D1.7.1 in local_daif_restore()
109 * interrupts with a lower priority than PMR is signaled in local_daif_restore()
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| D | kgdb.h | 43 * To expand a little on the "most versions of it"... when the gdb remote
44 * protocol for AArch64 was developed it depended on a statement in the
45 * Architecture Reference Manual that claimed "SPSR_ELx is a 32-bit register".
46 * and, as a result, allocated only 32-bits for the PSTATE in the remote
47 * protocol. In fact this statement is still present in ARM DDI 0487A.i.
49 * Unfortunately "is a 32-bit register" has a very special meaning for
51 * RES0.". RES0 is heavily used in the ARM architecture documents as a
52 * way to leave space for future architecture changes. So to translate a
54 * manuals, what "is a 32-bit register" actually means in this context is
55 * "is a 64-bit register but one with no meaning allocated to any of the
[all …]
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| D | cache.h | 97 * According to ARM ARM for ARMv8-A (ARM DDI 0487C.a),
|
| /kernel/linux/linux-6.6/arch/arm64/include/asm/ |
| D | kgdb.h | 43 * To expand a little on the "most versions of it"... when the gdb remote
44 * protocol for AArch64 was developed it depended on a statement in the
45 * Architecture Reference Manual that claimed "SPSR_ELx is a 32-bit register".
46 * and, as a result, allocated only 32-bits for the PSTATE in the remote
47 * protocol. In fact this statement is still present in ARM DDI 0487A.i.
49 * Unfortunately "is a 32-bit register" has a very special meaning for
51 * RES0.". RES0 is heavily used in the ARM architecture documents as a
52 * way to leave space for future architecture changes. So to translate a
54 * manuals, what "is a 32-bit register" actually means in this context is
55 * "is a 64-bit register but one with no meaning allocated to any of the
[all …]
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| D | daifflags.h | 34 /* Don't really care for a dsb here, we don't intend to enable IRQs */ in local_daif_mask()
98 * From the ARM ARM DDI 0487D.a, section D1.7.1 in local_daif_restore()
109 * interrupts with a lower priority than PMR is signaled in local_daif_restore()
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| D | cache.h | 99 * According to ARM ARM for ARMv8-A (ARM DDI 0487C.a),
|
| /kernel/linux/linux-6.6/drivers/hwtracing/coresight/ |
| D | coresight-cpu-debug.c | 122 * According to ARM DDI 0487A.k, before access external debug
215 * As described in ARM DDI 0487A.k, if the processing in debug_read_regs()
225 * A read of the EDPCSR normally has the side-effect of in debug_read_regs()
356 * In ARM DDI 0487A.k, the EDDEVID1.PCSROffset is used to in debug_init_arch_data()
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| /kernel/linux/linux-5.10/drivers/hwtracing/coresight/ |
| D | coresight-cpu-debug.c | 121 * According to ARM DDI 0487A.k, before access external debug
214 * As described in ARM DDI 0487A.k, if the processing in debug_read_regs()
224 * A read of the EDPCSR normally has the side-effect of in debug_read_regs()
355 * In ARM DDI 0487A.k, the EDDEVID1.PCSROffset is used to in debug_init_arch_data()
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| /kernel/linux/linux-6.6/drivers/acpi/arm64/ |
| D | gtdt.c | 121 * Return: true if the timer HW state is lost when a CPU enters an idle state,
148 * @platform_timer_count: It points to a integer variable which is used
212 * See ARM DDI 0487A.k_iss10775, page I1-5129, Table I1-3 in gtdt_parse_timer_block()
262 * See ARM DDI 0487A.k_iss10775, page I1-5130, Table I1-4 in gtdt_parse_timer_block()
296 * @timer_count: It points to a integer variable which is used for storing the
326 * Initialize a SBSA generic Watchdog platform device info from GTDT
345 pr_debug("found a Watchdog (0x%llx/0x%llx gsi:%u flags:0x%x).\n", in gtdt_import_sbsa_gwdt()
362 * Add a platform device named "sbsa-gwdt" to match the platform driver. in gtdt_import_sbsa_gwdt()
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| /kernel/linux/linux-5.10/drivers/acpi/arm64/ |
| D | gtdt.c | 121 * Return: true if the timer HW state is lost when a CPU enters an idle state,
148 * @platform_timer_count: It points to a integer variable which is used
212 * See ARM DDI 0487A.k_iss10775, page I1-5129, Table I1-3 in gtdt_parse_timer_block()
262 * See ARM DDI 0487A.k_iss10775, page I1-5130, Table I1-4 in gtdt_parse_timer_block()
296 * @timer_count: It points to a integer variable which is used for storing the
326 * Initialize a SBSA generic Watchdog platform device info from GTDT
345 pr_debug("found a Watchdog (0x%llx/0x%llx gsi:%u flags:0x%x).\n", in gtdt_import_sbsa_gwdt()
362 * Add a platform device named "sbsa-gwdt" to match the platform driver. in gtdt_import_sbsa_gwdt()
|