Home
last modified time | relevance | path

Searched +full:0 +full:x00000504 (Results 1 – 25 of 70) sorted by relevance

123

/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dtegra30-asus-nexus7-tilapia-memory-timings.dtsi13 emc-timings-0 {
17 nvidia,emc-auto-cal-interval = <0x001fffff>;
18 nvidia,emc-mode-1 = <0x80100002>;
19 nvidia,emc-mode-2 = <0x80200018>;
20 nvidia,emc-mode-reset = <0x80000b71>;
21 nvidia,emc-zcal-cnt-long = <0x00000040>;
25 0x0000001f /* EMC_RC */
26 0x00000069 /* EMC_RFC */
27 0x00000017 /* EMC_RAS */
28 0x00000007 /* EMC_RP */
[all …]
Dtegra30-asus-nexus7-grouper-memory-timings.dtsi5 emc-timings-0 {
6 nvidia,ram-code = <0>; /* Elpida EDJ2108EDBG-DJL-F */
12 0x00020001 /* MC_EMEM_ARB_CFG */
13 0xc0000020 /* MC_EMEM_ARB_OUTSTANDING_REQ */
14 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
15 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
16 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
17 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
18 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
19 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/nvidia/
Dtegra30-asus-nexus7-tilapia-memory-timings.dtsi13 emc-timings-0 {
17 nvidia,emc-auto-cal-interval = <0x001fffff>;
18 nvidia,emc-mode-1 = <0x80100002>;
19 nvidia,emc-mode-2 = <0x80200018>;
20 nvidia,emc-mode-reset = <0x80000b71>;
21 nvidia,emc-zcal-cnt-long = <0x00000040>;
25 0x0000001f /* EMC_RC */
26 0x00000069 /* EMC_RFC */
27 0x00000017 /* EMC_RAS */
28 0x00000007 /* EMC_RP */
[all …]
Dtegra30-asus-tf300t.dts75 reg = <0x10>;
94 mount-matrix = "0", "-1", "0",
95 "-1", "0", "0",
96 "0", "0", "-1";
100 mount-matrix = "-1", "0", "0",
101 "0", "1", "0",
102 "0", "0", "-1";
107 mount-matrix = "0", "-1", "0",
108 "-1", "0", "0",
109 "0", "0", "1";
[all …]
Dtegra30-asus-tf300tg.dts22 <TEGRA_GPIO(X, 0) GPIO_ACTIVE_HIGH>,
171 reg = <0x10>;
190 mount-matrix = "1", "0", "0",
191 "0", "-1", "0",
192 "0", "0", "-1";
196 mount-matrix = "-1", "0", "0",
197 "0", "1", "0",
198 "0", "0", "-1";
203 mount-matrix = "0", "-1", "0",
204 "-1", "0", "0",
[all …]
/kernel/linux/linux-5.10/sound/soc/codecs/
Dcs35l36.h16 #define CS35L36_FIRSTREG 0x00000000
17 #define CS35L36_LASTREG 0x00E037FC
18 #define CS35L36_SW_RESET 0x00000000
19 #define CS35L36_SW_REV 0x00000004
20 #define CS35L36_HW_REV 0x00000008
21 #define CS35L36_TESTKEY_CTRL 0x00000020
22 #define CS35L36_USERKEY_CTL 0x00000024
23 #define CS35L36_OTP_MEM30 0x00000478
24 #define CS35L36_OTP_CTRL1 0x00000500
25 #define CS35L36_OTP_CTRL2 0x00000504
[all …]
/kernel/linux/linux-6.6/sound/soc/codecs/
Dcs35l36.h16 #define CS35L36_FIRSTREG 0x00000000
17 #define CS35L36_LASTREG 0x00E037FC
18 #define CS35L36_SW_RESET 0x00000000
19 #define CS35L36_SW_REV 0x00000004
20 #define CS35L36_HW_REV 0x00000008
21 #define CS35L36_TESTKEY_CTRL 0x00000020
22 #define CS35L36_USERKEY_CTL 0x00000024
23 #define CS35L36_OTP_MEM30 0x00000478
24 #define CS35L36_OTP_CTRL1 0x00000500
25 #define CS35L36_OTP_CTRL2 0x00000504
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/memory-controllers/
Dnvidia,tegra30-emc.yaml35 const: 0
53 "^emc-timings-[0-9]+$":
62 "^timing-[0-9]+$":
75 minimum: 0
91 Mode Register 0.
98 minimum: 0
239 reg = <0x7000f400 0x400>;
240 interrupts = <0 78 4>;
247 #interconnect-cells = <0>;
255 nvidia,emc-auto-cal-interval = <0x001fffff>;
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/memory-controllers/
Dnvidia,tegra30-emc.yaml40 "^emc-timings-[0-9]+$":
49 "^timing-[0-9]+$":
62 minimum: 0
78 Mode Register 0.
85 minimum: 0
224 reg = <0x7000f400 0x400>;
225 interrupts = <0 78 4>;
236 nvidia,emc-auto-cal-interval = <0x001fffff>;
237 nvidia,emc-mode-1 = <0x80100002>;
238 nvidia,emc-mode-2 = <0x80200018>;
[all …]
/kernel/linux/linux-6.6/drivers/net/wireless/ath/ath11k/
Dhw.c21 case 0: in ath11k_hw_ipq8074_mac_from_pdev_id()
22 return 0; in ath11k_hw_ipq8074_mac_from_pdev_id()
71 config->rx_timeout_pri[0] = TARGET_RX_TIMEOUT_LO_PRI; in ath11k_init_wmi_config_qca6390()
80 config->num_mcast_groups = 0; in ath11k_init_wmi_config_qca6390()
81 config->num_mcast_table_elems = 0; in ath11k_init_wmi_config_qca6390()
82 config->mcast2ucast_mode = 0; in ath11k_init_wmi_config_qca6390()
84 config->num_wds_entries = 0; in ath11k_init_wmi_config_qca6390()
85 config->dma_burst_size = 0; in ath11k_init_wmi_config_qca6390()
86 config->rx_skip_defrag_timeout_dup_detection_check = 0; in ath11k_init_wmi_config_qca6390()
89 config->num_msdu_desc = 0x400; in ath11k_init_wmi_config_qca6390()
[all …]
/kernel/linux/linux-6.6/drivers/net/ipa/reg/
Dipa_reg-v3.1.c11 [COMP_CFG_ENABLE] = BIT(0),
19 REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
22 [CLKON_RX] = BIT(0),
42 REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
45 [ROUTE_DIS] = BIT(0),
55 REG_FIELDS(ROUTE, route, 0x00000048);
58 [MEM_SIZE] = GENMASK(15, 0),
62 REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054);
65 [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),
70 REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074);
[all …]
Dipa_reg-v3.5.1.c11 [COMP_CFG_ENABLE] = BIT(0),
19 REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
22 [CLKON_RX] = BIT(0),
47 REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
50 [ROUTE_DIS] = BIT(0),
60 REG_FIELDS(ROUTE, route, 0x00000048);
63 [MEM_SIZE] = GENMASK(15, 0),
67 REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054);
70 [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),
75 REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074);
[all …]
Dipa_reg-v4.2.c11 /* Bit 0 reserved */
32 REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
35 [CLKON_RX] = BIT(0),
68 REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
71 [ROUTE_DIS] = BIT(0),
81 REG_FIELDS(ROUTE, route, 0x00000048);
84 [MEM_SIZE] = GENMASK(15, 0),
88 REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054);
91 [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),
96 REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074);
[all …]
Dipa_reg-v4.7.c11 [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),
33 REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
36 [CLKON_RX] = BIT(0),
70 REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
73 [ROUTE_DIS] = BIT(0),
83 REG_FIELDS(ROUTE, route, 0x00000048);
86 [MEM_SIZE] = GENMASK(15, 0),
90 REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054);
93 [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),
98 REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074);
[all …]
Dipa_reg-v4.9.c11 [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),
38 REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
41 [CLKON_RX] = BIT(0),
75 REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
78 [ROUTE_DIS] = BIT(0),
88 REG_FIELDS(ROUTE, route, 0x00000048);
91 [MEM_SIZE] = GENMASK(15, 0),
95 REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054);
98 [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),
103 REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074);
[all …]
Dipa_reg-v4.11.c11 [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),
39 REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
42 [CLKON_RX] = BIT(0),
76 REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
79 [ROUTE_DIS] = BIT(0),
89 REG_FIELDS(ROUTE, route, 0x00000048);
92 [MEM_SIZE] = GENMASK(15, 0),
96 REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054);
99 [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),
104 REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074);
[all …]
Dipa_reg-v5.0.c11 [MAX_PIPES] = GENMASK(7, 0),
17 REG_FIELDS(FLAVOR_0, flavor_0, 0x00000000);
20 [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),
48 REG_FIELDS(COMP_CFG, comp_cfg, 0x0000002c);
51 [CLKON_RX] = BIT(0),
85 REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000034);
88 [ROUTE_DEF_PIPE] = GENMASK(7, 0),
97 REG_FIELDS(ROUTE, route, 0x00000038);
100 [MEM_SIZE] = GENMASK(15, 0),
104 REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000040);
[all …]
Dipa_reg-v4.5.c11 /* Bit 0 reserved */
33 REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
36 [CLKON_RX] = BIT(0),
70 REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
73 [ROUTE_DIS] = BIT(0),
83 REG_FIELDS(ROUTE, route, 0x00000048);
86 [MEM_SIZE] = GENMASK(15, 0),
90 REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054);
93 [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),
98 REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074);
[all …]
/kernel/linux/linux-5.10/drivers/net/ipa/
Dipa_reg.h68 #define IPA_REG_ENABLED_PIPES_OFFSET 0x00000038
70 #define IPA_REG_COMP_CFG_OFFSET 0x0000003c
71 #define ENABLE_FMASK GENMASK(0, 0)
90 #define IPA_REG_CLKON_CFG_OFFSET 0x00000044
91 #define RX_FMASK GENMASK(0, 0)
122 #define IPA_REG_ROUTE_OFFSET 0x00000048
123 #define ROUTE_DIS_FMASK GENMASK(0, 0)
130 #define IPA_REG_SHARED_MEM_SIZE_OFFSET 0x00000054
131 #define SHARED_MEM_SIZE_FMASK GENMASK(15, 0)
134 #define IPA_REG_QSB_MAX_WRITES_OFFSET 0x00000074
[all …]
/kernel/linux/linux-5.10/sound/pci/cs46xx/
Dcs46xx.h25 #define BA0_HISR 0x00000000
26 #define BA0_HSR0 0x00000004
27 #define BA0_HICR 0x00000008
28 #define BA0_DMSR 0x00000100
29 #define BA0_HSAR 0x00000110
30 #define BA0_HDAR 0x00000114
31 #define BA0_HDMR 0x00000118
32 #define BA0_HDCR 0x0000011C
33 #define BA0_PFMC 0x00000200
34 #define BA0_PFCV1 0x00000204
[all …]
/kernel/linux/linux-6.6/sound/pci/cs46xx/
Dcs46xx.h25 #define BA0_HISR 0x00000000
26 #define BA0_HSR0 0x00000004
27 #define BA0_HICR 0x00000008
28 #define BA0_DMSR 0x00000100
29 #define BA0_HSAR 0x00000110
30 #define BA0_HDAR 0x00000114
31 #define BA0_HDMR 0x00000118
32 #define BA0_HDCR 0x0000011C
33 #define BA0_PFMC 0x00000200
34 #define BA0_PFCV1 0x00000204
[all …]
/kernel/linux/linux-6.6/include/sound/
Dcs35l41.h16 #define CS35L41_FIRSTREG 0x00000000
17 #define CS35L41_LASTREG 0x03804FE8
18 #define CS35L41_DEVID 0x00000000
19 #define CS35L41_REVID 0x00000004
20 #define CS35L41_FABID 0x00000008
21 #define CS35L41_RELID 0x0000000C
22 #define CS35L41_OTPID 0x00000010
23 #define CS35L41_SFT_RESET 0x00000020
24 #define CS35L41_TEST_KEY_CTL 0x00000040
25 #define CS35L41_USER_KEY_CTL 0x00000044
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/xilinx/
Dxilinx_axienet.h31 #define XAE_OPTION_PROMISC (1 << 0)
74 #define XAXIDMA_TX_CR_OFFSET 0x00000000 /* Channel control */
75 #define XAXIDMA_TX_SR_OFFSET 0x00000004 /* Status */
76 #define XAXIDMA_TX_CDESC_OFFSET 0x00000008 /* Current descriptor pointer */
77 #define XAXIDMA_TX_TDESC_OFFSET 0x00000010 /* Tail descriptor pointer */
79 #define XAXIDMA_RX_CR_OFFSET 0x00000030 /* Channel control */
80 #define XAXIDMA_RX_SR_OFFSET 0x00000034 /* Status */
81 #define XAXIDMA_RX_CDESC_OFFSET 0x00000038 /* Current descriptor pointer */
82 #define XAXIDMA_RX_TDESC_OFFSET 0x00000040 /* Tail descriptor pointer */
84 #define XAXIDMA_CR_RUNSTOP_MASK 0x00000001 /* Start/stop DMA channel */
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/rockchip/
Drockchip_vop_reg.h11 #define RK3288_REG_CFG_DONE 0x0000
12 #define RK3288_VERSION_INFO 0x0004
13 #define RK3288_SYS_CTRL 0x0008
14 #define RK3288_SYS_CTRL1 0x000c
15 #define RK3288_DSP_CTRL0 0x0010
16 #define RK3288_DSP_CTRL1 0x0014
17 #define RK3288_DSP_BG 0x0018
18 #define RK3288_MCU_CTRL 0x001c
19 #define RK3288_INTR_CTRL0 0x0020
20 #define RK3288_INTR_CTRL1 0x0024
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/xilinx/
Dxilinx_axienet.h31 #define XAE_OPTION_PROMISC (1 << 0)
74 #define XAXIDMA_TX_CR_OFFSET 0x00000000 /* Channel control */
75 #define XAXIDMA_TX_SR_OFFSET 0x00000004 /* Status */
76 #define XAXIDMA_TX_CDESC_OFFSET 0x00000008 /* Current descriptor pointer */
77 #define XAXIDMA_TX_TDESC_OFFSET 0x00000010 /* Tail descriptor pointer */
79 #define XAXIDMA_RX_CR_OFFSET 0x00000030 /* Channel control */
80 #define XAXIDMA_RX_SR_OFFSET 0x00000034 /* Status */
81 #define XAXIDMA_RX_CDESC_OFFSET 0x00000038 /* Current descriptor pointer */
82 #define XAXIDMA_RX_TDESC_OFFSET 0x00000040 /* Tail descriptor pointer */
84 #define XAXIDMA_CR_RUNSTOP_MASK 0x00000001 /* Start/stop DMA channel */
[all …]

123