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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/
Dqcom,sc8280xp-qmp-ufs-phy.yaml67 const: 0
141 reg = <0x01d87000 0x1000>;
148 resets = <&ufs_mem_hc 0>;
154 #phy-cells = <0>;
/kernel/linux/linux-5.10/arch/arm64/boot/dts/qcom/
Dsm8150.dtsi28 #clock-cells = <0>;
35 #clock-cells = <0>;
43 #size-cells = <0>;
45 CPU0: cpu@0 {
48 reg = <0x0 0x0>;
51 qcom,freq-domain = <&cpufreq_hw 0>;
65 reg = <0x0 0x100>;
68 qcom,freq-domain = <&cpufreq_hw 0>;
80 reg = <0x0 0x200>;
83 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsm8250.dtsi71 #clock-cells = <0>;
79 #clock-cells = <0>;
85 #size-cells = <0>;
87 CPU0: cpu@0 {
90 reg = <0x0 0x0>;
93 qcom,freq-domain = <&cpufreq_hw 0>;
107 reg = <0x0 0x100>;
110 qcom,freq-domain = <&cpufreq_hw 0>;
121 reg = <0x0 0x200>;
124 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsdm845.dtsi73 reg = <0 0x80000000 0 0>;
82 reg = <0 0x85700000 0 0x600000>;
87 reg = <0 0x85e00000 0 0x100000>;
92 reg = <0 0x85fc0000 0 0x20000>;
98 reg = <0x0 0x85fe0000 0 0x20000>;
103 reg = <0x0 0x86000000 0 0x200000>;
108 reg = <0 0x86200000 0 0x2d00000>;
114 reg = <0 0x88f00000 0 0x200000>;
122 reg = <0 0x8ab00000 0 0x1400000>;
127 reg = <0 0x8bf00000 0 0x500000>;
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/qcom/
Dsa8775p.dtsi25 #clock-cells = <0>;
30 #clock-cells = <0>;
36 #size-cells = <0>;
38 CPU0: cpu@0 {
41 reg = <0x0 0x0>;
43 qcom,freq-domain = <&cpufreq_hw 0>;
61 reg = <0x0 0x100>;
63 qcom,freq-domain = <&cpufreq_hw 0>;
76 reg = <0x0 0x200>;
78 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsm6350.dtsi31 #clock-cells = <0>;
39 #clock-cells = <0>;
45 #size-cells = <0>;
47 CPU0: cpu@0 {
50 reg = <0x0 0x0>;
51 clocks = <&cpufreq_hw 0>;
56 qcom,freq-domain = <&cpufreq_hw 0>;
80 reg = <0x0 0x100>;
81 clocks = <&cpufreq_hw 0>;
86 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsc8180x.dtsi27 #clock-cells = <0>;
33 #clock-cells = <0>;
41 #size-cells = <0>;
43 CPU0: cpu@0 {
46 reg = <0x0 0x0>;
50 qcom,freq-domain = <&cpufreq_hw 0>;
57 clocks = <&cpufreq_hw 0>;
75 reg = <0x0 0x100>;
79 qcom,freq-domain = <&cpufreq_hw 0>;
86 clocks = <&cpufreq_hw 0>;
[all …]
Dsm8350.dtsi36 #clock-cells = <0>;
44 #clock-cells = <0>;
50 #size-cells = <0>;
52 CPU0: cpu@0 {
55 reg = <0x0 0x0>;
56 clocks = <&cpufreq_hw 0>;
59 qcom,freq-domain = <&cpufreq_hw 0>;
79 reg = <0x0 0x100>;
80 clocks = <&cpufreq_hw 0>;
83 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsm8150.dtsi30 #clock-cells = <0>;
37 #clock-cells = <0>;
45 #size-cells = <0>;
47 CPU0: cpu@0 {
50 reg = <0x0 0x0>;
51 clocks = <&cpufreq_hw 0>;
56 qcom,freq-domain = <&cpufreq_hw 0>;
58 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
79 reg = <0x0 0x100>;
80 clocks = <&cpufreq_hw 0>;
[all …]
Dsm8450.dtsi36 #clock-cells = <0>;
42 #clock-cells = <0>;
49 #size-cells = <0>;
51 CPU0: cpu@0 {
54 reg = <0x0 0x0>;
59 qcom,freq-domain = <&cpufreq_hw 0>;
61 clocks = <&cpufreq_hw 0>;
78 reg = <0x0 0x100>;
83 qcom,freq-domain = <&cpufreq_hw 0>;
85 clocks = <&cpufreq_hw 0>;
[all …]
Dsc8280xp.dtsi32 #clock-cells = <0>;
37 #clock-cells = <0>;
44 #size-cells = <0>;
46 CPU0: cpu@0 {
49 reg = <0x0 0x0>;
50 clocks = <&cpufreq_hw 0>;
56 qcom,freq-domain = <&cpufreq_hw 0>;
76 reg = <0x0 0x100>;
77 clocks = <&cpufreq_hw 0>;
83 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsdm845.dtsi76 #clock-cells = <0>;
83 #clock-cells = <0>;
90 #size-cells = <0>;
92 CPU0: cpu@0 {
95 reg = <0x0 0x0>;
96 clocks = <&cpufreq_hw 0>;
100 qcom,freq-domain = <&cpufreq_hw 0>;
124 reg = <0x0 0x100>;
125 clocks = <&cpufreq_hw 0>;
129 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsm8250.dtsi81 #clock-cells = <0>;
89 #clock-cells = <0>;
95 #size-cells = <0>;
97 CPU0: cpu@0 {
100 reg = <0x0 0x0>;
101 clocks = <&cpufreq_hw 0>;
108 qcom,freq-domain = <&cpufreq_hw 0>;
110 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
116 cache-size = <0x20000>;
122 cache-size = <0x400000>;
[all …]