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12

/kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/inc/
Dsmu_v12_0.h29 #define MP0_Public 0x03800000
30 #define MP0_SRAM 0x03900000
31 #define MP1_Public 0x03b00000
32 #define MP1_SRAM 0x03c00004
Dsmu_v11_0.h28 #define SMU11_DRIVER_IF_VERSION_INV 0xFFFFFFFF
29 #define SMU11_DRIVER_IF_VERSION_ARCT 0x17
30 #define SMU11_DRIVER_IF_VERSION_NV10 0x36
31 #define SMU11_DRIVER_IF_VERSION_NV12 0x36
32 #define SMU11_DRIVER_IF_VERSION_NV14 0x36
33 #define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x39
34 #define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0x5
37 #define MP0_Public 0x03800000
38 #define MP0_SRAM 0x03900000
39 #define MP1_Public 0x03b00000
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/pm/swsmu/inc/
Dsmu_v12_0.h29 #define MP0_Public 0x03800000
30 #define MP0_SRAM 0x03900000
31 #define MP1_Public 0x03b00000
32 #define MP1_SRAM 0x03c00004
Dsmu_v13_0.h31 #define MP0_Public 0x03800000
32 #define MP0_SRAM 0x03900000
33 #define MP1_Public 0x03b00000
34 #define MP1_SRAM 0x03c00004
37 #define smnMP1_FIRMWARE_FLAGS 0x3010024
38 #define smnMP1_V13_0_4_FIRMWARE_FLAGS 0x3010028
39 #define smnMP0_FW_INTF 0x30101c0
40 #define smnMP1_PUB_CTRL 0x3010b14
42 #define TEMP_RANGE_MIN (0)
45 #define SMU13_TOOL_SIZE 0x19000
[all …]
Dsmu_v11_0.h28 #define SMU11_DRIVER_IF_VERSION_INV 0xFFFFFFFF
29 #define SMU11_DRIVER_IF_VERSION_ARCT 0x17
30 #define SMU11_DRIVER_IF_VERSION_NV10 0x37
31 #define SMU11_DRIVER_IF_VERSION_NV12 0x38
32 #define SMU11_DRIVER_IF_VERSION_NV14 0x38
33 #define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x40
34 #define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0xE
35 #define SMU11_DRIVER_IF_VERSION_VANGOGH 0x03
36 #define SMU11_DRIVER_IF_VERSION_Dimgrey_Cavefish 0xF
37 #define SMU11_DRIVER_IF_VERSION_Beige_Goby 0xD
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/pinctrl/
Dqcom,sm7150-tlmm.yaml74 - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-8])$"
122 reg = <0x03500000 0x300000>,
123 <0x03900000 0x300000>,
124 <0x03d00000 0x300000>;
127 gpio-ranges = <&tlmm 0 0 120>;
Dqcom,sc7180-pinctrl.yaml71 - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-8])$"
123 reg = <0x03500000 0x300000>,
124 <0x03900000 0x300000>,
125 <0x03d00000 0x300000>;
132 gpio-ranges = <&tlmm 0 0 120>;
Dqcom,sm8150-pinctrl.yaml72 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-6][0-9]|17[0-4])$"
124 reg = <0x03100000 0x300000>,
125 <0x03500000 0x300000>,
126 <0x03900000 0x300000>,
127 <0x03d00000 0x300000>;
130 gpio-ranges = <&tlmm 0 0 176>;
Dqcom,sdm630-pinctrl.yaml77 - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-3])$"
141 reg = <0x03100000 0x400000>,
142 <0x03500000 0x400000>,
143 <0x03900000 0x400000>;
147 gpio-ranges = <&tlmm 0 0 114>;
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/powerplay/smumgr/
Dsmu9_smumgr.c31 #define MP0_Public 0x03800000
32 #define MP0_SRAM 0x03900000
33 #define MP1_Public 0x03b00000
34 #define MP1_SRAM 0x03c00004
36 …_FIRMWARE_FLAGS 0x3010028
44 (smnMP1_FIRMWARE_FLAGS & 0xffffffff)); in smu9_is_smc_ram_running()
65 reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_103); in smu9_wait_for_response()
68 0, MP1_C2PMSG_103__CONTENT_MASK); in smu9_wait_for_response()
73 return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_103); in smu9_wait_for_response()
75 reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); in smu9_wait_for_response()
[all …]
Dsmu10_smumgr.c41 #define MP0_Public 0x03800000
42 #define MP0_SRAM 0x03900000
43 #define MP1_Public 0x03b00000
44 #define MP1_SRAM 0x03c00004
46 #define smnMP1_FIRMWARE_FLAGS 0x3010028
54 reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); in smu10_wait_for_response()
57 0, MP1_C2PMSG_90__CONTENT_MASK); in smu10_wait_for_response()
59 return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90); in smu10_wait_for_response()
67 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg); in smu10_send_msg_to_smc_without_waiting()
69 return 0; in smu10_send_msg_to_smc_without_waiting()
[all …]
Dvega20_smumgr.c39 #define MP0_Public 0x03800000
40 #define MP0_SRAM 0x03900000
41 #define MP1_Public 0x03b00000
42 #define MP1_SRAM 0x03c00004
45 #define smnMP1_FIRMWARE_FLAGS 0x3010024
46 #define smnMP0_FW_INTF 0x30101c0
47 #define smnMP1_PUB_CTRL 0x3010b14
55 (smnMP1_FIRMWARE_FLAGS & 0xffffffff)); in vega20_is_smc_ram_running()
75 reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); in vega20_wait_for_response()
78 0, MP1_C2PMSG_90__CONTENT_MASK); in vega20_wait_for_response()
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/pm/powerplay/smumgr/
Dsmu9_smumgr.c32 #define MP0_Public 0x03800000
33 #define MP0_SRAM 0x03900000
34 #define MP1_Public 0x03b00000
35 #define MP1_SRAM 0x03c00004
37 …_FIRMWARE_FLAGS 0x3010028
45 (smnMP1_FIRMWARE_FLAGS & 0xffffffff)); in smu9_is_smc_ram_running()
66 reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_103); in smu9_wait_for_response()
69 0, MP1_C2PMSG_103__CONTENT_MASK); in smu9_wait_for_response()
74 return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_103); in smu9_wait_for_response()
76 reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); in smu9_wait_for_response()
[all …]
Dsmu10_smumgr.c41 #define MP0_Public 0x03800000
42 #define MP0_SRAM 0x03900000
43 #define MP1_Public 0x03b00000
44 #define MP1_SRAM 0x03c00004
46 #define smnMP1_FIRMWARE_FLAGS 0x3010028
54 reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); in smu10_wait_for_response()
57 0, MP1_C2PMSG_90__CONTENT_MASK); in smu10_wait_for_response()
59 return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90); in smu10_wait_for_response()
67 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg); in smu10_send_msg_to_smc_without_waiting()
69 return 0; in smu10_send_msg_to_smc_without_waiting()
[all …]
Dvega20_smumgr.c39 #define MP0_Public 0x03800000
40 #define MP0_SRAM 0x03900000
41 #define MP1_Public 0x03b00000
42 #define MP1_SRAM 0x03c00004
45 #define smnMP1_FIRMWARE_FLAGS 0x3010024
46 #define smnMP0_FW_INTF 0x30101c0
47 #define smnMP1_PUB_CTRL 0x3010b14
55 (smnMP1_FIRMWARE_FLAGS & 0xffffffff)); in vega20_is_smc_ram_running()
75 reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); in vega20_wait_for_response()
78 0, MP1_C2PMSG_90__CONTENT_MASK); in vega20_wait_for_response()
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pinctrl/
Dqcom,sm8150-pinctrl.txt178 reg = <0x03100000 0x300000>,
179 <0x03500000 0x300000>,
180 <0x03900000 0x300000>,
181 <0x03D00000 0x300000>;
186 gpio-ranges = <&tlmm 0 0 175>;
187 gpio-reserved-ranges = <0 4>, <126 4>;
/kernel/linux/linux-5.10/arch/arm64/boot/dts/qcom/
Dsdm660.dtsi21 #clock-cells = <0>;
28 #clock-cells = <0>;
36 #size-cells = <0>;
41 reg = <0x0 0x100>;
60 reg = <0x0 0x101>;
75 reg = <0x0 0x102>;
90 reg = <0x0 0x103>;
102 CPU4: cpu@0 {
105 reg = <0x0 0x0>;
124 reg = <0x0 0x1>;
[all …]
Dsdm630.dtsi22 #clock-cells = <0>;
29 #clock-cells = <0>;
37 #size-cells = <0>;
42 reg = <0x0 0x100>;
61 reg = <0x0 0x101>;
76 reg = <0x0 0x102>;
91 reg = <0x0 0x103>;
103 CPU4: cpu@0 {
106 reg = <0x0 0x0>;
125 reg = <0x0 0x1>;
[all …]
Dsm8150.dtsi28 #clock-cells = <0>;
35 #clock-cells = <0>;
43 #size-cells = <0>;
45 CPU0: cpu@0 {
48 reg = <0x0 0x0>;
51 qcom,freq-domain = <&cpufreq_hw 0>;
65 reg = <0x0 0x100>;
68 qcom,freq-domain = <&cpufreq_hw 0>;
80 reg = <0x0 0x200>;
83 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsc7180.dtsi60 #clock-cells = <0>;
66 #clock-cells = <0>;
76 reg = <0x0 0x80000000 0x0 0x600000>;
81 reg = <0x0 0x80600000 0x0 0x200000>;
86 reg = <0x0 0x80800000 0x0 0x20000>;
91 reg = <0x0 0x80820000 0x0 0x20000>;
97 reg = <0x0 0x808ff000 0x0 0x1000>;
102 reg = <0x0 0x80900000 0x0 0x200000>;
107 reg = <0x0 0x80b00000 0x0 0x3900000>;
113 reg = <0x0 0x84400000 0x0 0x200000>;
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/freescale/
Dfsl-lx2160a.dtsi11 /memreserve/ 0x80000000 0x00010000;
25 #size-cells = <0>;
28 cpu0: cpu@0 {
32 reg = <0x0>;
33 clocks = <&clockgen 1 0>;
34 d-cache-size = <0x8000>;
37 i-cache-size = <0xC000>;
49 reg = <0x1>;
50 clocks = <&clockgen 1 0>;
51 d-cache-size = <0x8000>;
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/freescale/
Dfsl-lx2160a.dtsi12 /memreserve/ 0x80000000 0x00010000;
26 #size-cells = <0>;
29 cpu0: cpu@0 {
33 reg = <0x0>;
34 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
35 d-cache-size = <0x8000>;
38 i-cache-size = <0xC000>;
50 reg = <0x1>;
51 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
52 d-cache-size = <0x8000>;
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/qcom/
Dsdm630.dtsi33 #clock-cells = <0>;
40 #clock-cells = <0>;
48 #size-cells = <0>;
53 reg = <0x0 0x100>;
73 reg = <0x0 0x101>;
88 reg = <0x0 0x102>;
103 reg = <0x0 0x103>;
115 CPU4: cpu@0 {
118 reg = <0x0 0x0>;
138 reg = <0x0 0x1>;
[all …]
Dsc7180.dtsi62 #clock-cells = <0>;
68 #clock-cells = <0>;
74 #size-cells = <0>;
76 CPU0: cpu@0 {
79 reg = <0x0 0x0>;
80 clocks = <&cpufreq_hw 0>;
91 qcom,freq-domain = <&cpufreq_hw 0>;
108 reg = <0x0 0x100>;
109 clocks = <&cpufreq_hw 0>;
120 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsm8150.dtsi30 #clock-cells = <0>;
37 #clock-cells = <0>;
45 #size-cells = <0>;
47 CPU0: cpu@0 {
50 reg = <0x0 0x0>;
51 clocks = <&cpufreq_hw 0>;
56 qcom,freq-domain = <&cpufreq_hw 0>;
58 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
79 reg = <0x0 0x100>;
80 clocks = <&cpufreq_hw 0>;
[all …]

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