Searched +full:0 +full:x0d040000 (Results 1 – 9 of 9) sorted by relevance
25 #define SONIC83934_ADDR IOADDR(0x0d030000)33 #define IRQ_PCI_A (XCHAL_NUM_INTERRUPTS + 0)41 #define XT2000_LED_ADDR IOADDR(0x0d040000)
48 interrupts = <3 0>;49 reg = <0x0d040000 0x1000>;51 #size-cells = <0>;56 reg = <0x57 0x0 0x10>;57 pagesize = <0x8>;
20 pattern: "^i3c-master@[0-9a-f]+$"40 const: 063 "@[0-9a-f]+$":83 minimum: 084 maximum: 0x7f85 - const: 090 * 0: I2C device has a 50 ns spike filter98 * 0: FM+ mode100 bit[3:0]: device type101 * 0-15: reserved[all …]
16 - #size-cells: shall be set to 029 i3c-master@0d040000 {33 interrupts = <3 0>;34 reg = <0x0d040000 0x1000>;36 #size-cells = <0>;41 reg = <0x52 0x0 0x10>;
11 - #size-cells - should be <0>.46 + second cell: shall be 051 * 0: I2C device has a 50 ns spike filter59 * 0: FM+ mode62 bit[3:0]: device type63 * 0-15: reserved90 + first cell : encodes the static I2C address. Should be 0 if the device does91 not have one (0 is not a valid I2C address).105 address (first cell of the reg property != 0).114 interrupts = <3 0>;[all …]
20 /*/memreserve/ 0x10000000 0x0004000;*/ /* DSP RAM */34 reg = <0x00000000 0x01800000 /* MEM1 24MB 1T-SRAM */35 0x10000000 0x04000000>; /* MEM2 64MB GDDR3 */40 #size-cells = <0>;42 PowerPC,broadway@0 {44 reg = <0>;60 ranges = <0x0c000000 0x0c000000 0x0100000061 0x0d000000 0x0d000000 0x0080000062 0x0d800000 0x0d800000 0x00800000>;68 reg = <0x0c002000 0x100>;[all …]
27 #define ERRLOGGER_0_ID_COREID_0 0x0000000028 #define ERRLOGGER_0_ID_REVISIONID_0 0x0000000429 #define ERRLOGGER_0_FAULTEN_0 0x0000000830 #define ERRLOGGER_0_ERRVLD_0 0x0000000c31 #define ERRLOGGER_0_ERRCLR_0 0x0000001032 #define ERRLOGGER_0_ERRLOG0_0 0x0000001433 #define ERRLOGGER_0_ERRLOG1_0 0x0000001834 #define ERRLOGGER_0_RSVD_00_0 0x0000001c35 #define ERRLOGGER_0_ERRLOG3_0 0x0000002036 #define ERRLOGGER_0_ERRLOG4_0 0x00000024[all …]