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/kernel/linux/linux-6.6/include/linux/mtd/
Ddoc2000.h17 #define DoC_Sig1 0
20 #define DoC_ChipID 0x1000
21 #define DoC_DOCStatus 0x1001
22 #define DoC_DOCControl 0x1002
23 #define DoC_FloorSelect 0x1003
24 #define DoC_CDSNControl 0x1004
25 #define DoC_CDSNDeviceSelect 0x1005
26 #define DoC_ECCConf 0x1006
27 #define DoC_2k_ECCStatus 0x1007
29 #define DoC_CDSNSlowIO 0x100d
[all …]
/kernel/linux/linux-5.10/include/linux/mtd/
Ddoc2000.h17 #define DoC_Sig1 0
20 #define DoC_ChipID 0x1000
21 #define DoC_DOCStatus 0x1001
22 #define DoC_DOCControl 0x1002
23 #define DoC_FloorSelect 0x1003
24 #define DoC_CDSNControl 0x1004
25 #define DoC_CDSNDeviceSelect 0x1005
26 #define DoC_ECCConf 0x1006
27 #define DoC_2k_ECCStatus 0x1007
29 #define DoC_CDSNSlowIO 0x100d
[all …]
/kernel/linux/linux-5.10/drivers/media/dvb-frontends/
Datbm8830_priv.h19 #define REG_CHIP_ID 0x0000
20 #define REG_TUNER_BASEBAND 0x0001
21 #define REG_DEMOD_RUN 0x0004
22 #define REG_DSP_RESET 0x0005
23 #define REG_RAM_RESET 0x0006
24 #define REG_ADC_RESET 0x0007
25 #define REG_TSPORT_RESET 0x0008
26 #define REG_BLKERR_POL 0x000C
27 #define REG_I2C_GATE 0x0103
28 #define REG_TS_SAMPLE_EDGE 0x0301
[all …]
/kernel/linux/linux-6.6/drivers/media/dvb-frontends/
Datbm8830_priv.h19 #define REG_CHIP_ID 0x0000
20 #define REG_TUNER_BASEBAND 0x0001
21 #define REG_DEMOD_RUN 0x0004
22 #define REG_DSP_RESET 0x0005
23 #define REG_RAM_RESET 0x0006
24 #define REG_ADC_RESET 0x0007
25 #define REG_TSPORT_RESET 0x0008
26 #define REG_BLKERR_POL 0x000C
27 #define REG_I2C_GATE 0x0103
28 #define REG_TS_SAMPLE_EDGE 0x0301
[all …]
/kernel/linux/linux-6.6/drivers/mmc/host/
Dsdhci-pci-dwc-mshc.c15 #define SDHCI_VENDOR_PTR_R 0xE8
18 #define SDHC_GPIO_OUT 0x34
19 #define SDHC_AT_CTRL_R 0x40
20 #define SDHC_SW_TUNE_EN 0x00000010
23 #define SDHC_MMCM_DIV_REG 0x1020
24 #define DIV_REG_100_MHZ 0x1145
25 #define DIV_REG_200_MHZ 0x1083
26 #define SDHC_MMCM_CLKFBOUT 0x1024
27 #define CLKFBOUT_100_MHZ 0x0000
28 #define CLKFBOUT_200_MHZ 0x0080
[all …]
/kernel/linux/linux-5.10/drivers/mmc/host/
Dsdhci-pci-dwc-mshc.c15 #define SDHCI_VENDOR_PTR_R 0xE8
18 #define SDHC_GPIO_OUT 0x34
19 #define SDHC_AT_CTRL_R 0x40
20 #define SDHC_SW_TUNE_EN 0x00000010
23 #define SDHC_MMCM_DIV_REG 0x1020
24 #define DIV_REG_100_MHZ 0x1145
25 #define DIV_REG_200_MHZ 0x1083
26 #define SDHC_MMCM_CLKFBOUT 0x1024
27 #define CLKFBOUT_100_MHZ 0x0000
28 #define CLKFBOUT_200_MHZ 0x0080
[all …]
/kernel/linux/linux-6.6/arch/powerpc/kernel/
Dhead_40x.S84 . = 0xc0
110 stw r10,crit_r10@l(0) /* save two registers to work with */
111 stw r11,crit_r11@l(0)
114 stw r10,crit_srr0@l(0)
115 stw r11,crit_srr1@l(0)
118 stw r10,crit_dear@l(0)
119 stw r11,crit_esr@l(0)
129 1: stw r1,crit_r1@l(0)
141 lwz r11,crit_r1@l(0)
143 stw r11,0(r1)
[all …]
/kernel/linux/linux-5.10/arch/powerpc/kernel/
Dhead_40x.S83 . = 0xc0
105 stw r10,crit_r10@l(0); /* save two registers to work with */\
106 stw r11,crit_r11@l(0); \
131 stw r1,0(r11); \
133 rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\
165 * 0x0100 - Critical Interrupt Exception
167 CRITICAL_EXCEPTION(0x0100, CriticalInterrupt, unknown_exception)
170 * 0x0200 - Machine Check Exception
172 CRITICAL_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
175 * 0x0300 - Data Storage Exception
[all …]
/kernel/linux/linux-6.6/drivers/accel/habanalabs/include/gaudi2/asic_reg/
Ddcore0_tpc0_eml_spmu_regs.h23 #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR0_EL0 0x1000
25 #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR1_EL0 0x1008
27 #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR2_EL0 0x1010
29 #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR3_EL0 0x1018
31 #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR4_EL0 0x1020
33 #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR5_EL0 0x1028
35 #define mmDCORE0_TPC0_EML_SPMU_PMCCNTR_L_EL0 0x10F8
37 #define mmDCORE0_TPC0_EML_SPMU_PMCCNTR_H_EL0 0x10FC
39 #define mmDCORE0_TPC0_EML_SPMU_PMTRC 0x1200
41 #define mmDCORE0_TPC0_EML_SPMU_TRC_CTRL_HOST 0x1204
[all …]
/kernel/linux/linux-6.6/drivers/clk/qcom/
Dgpucc-msm8998.c35 .halt_reg = 0x1020,
37 .enable_reg = 0x1020,
38 .enable_mask = BIT(0),
52 { 249600000, 2000000000, 0 },
57 { 0x0, 1 },
58 { 0x1, 2 },
59 { 0x3, 4 },
60 { 0x7, 8 },
65 .offset = 0x0,
78 .offset = 0x0,
[all …]
Dgpucc-sdm660.c38 .halt_reg = 0x1020,
40 .enable_reg = 0x1020,
41 .enable_mask = BIT(0),
55 { 1000000000, 2000000000, 0 },
61 .offset = 0x0,
76 .offset = 0x40,
91 { P_GPU_XO, 0 },
107 .cmd_rcgr = 0x1070,
108 .mnd_width = 0,
127 .halt_reg = 0x1098,
[all …]
/kernel/linux/linux-5.10/drivers/clk/qcom/
Dgpucc-msm8998.c36 .halt_reg = 0x1020,
38 .enable_reg = 0x1020,
39 .enable_mask = BIT(0),
54 { 0x0, 1 },
55 { 0x1, 2 },
56 { 0x3, 4 },
57 { 0x7, 8 },
62 .offset = 0x0,
73 .offset = 0x0,
88 { P_XO, 0 },
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dsprd,sc9863a-clk.yaml82 reg = <0x21500000 0x1000>;
91 reg = <0x20e00000 0x4000>;
94 ranges = <0 0x20e00000 0x4000>;
96 apahb_gate: apahb-gate@0 {
98 reg = <0x0 0x1020>;
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/
Dsprd,sc9863a-clk.yaml81 reg = <0x21500000 0x1000>;
90 reg = <0x20e00000 0x4000>;
93 ranges = <0 0x20e00000 0x4000>;
95 apahb_gate: apahb-gate@0 {
97 reg = <0x0 0x1020>;
/kernel/linux/linux-6.6/drivers/clk/samsung/
Dclk-exynos5260.h15 #define MUX_SEL_AUD 0x0200
16 #define MUX_ENABLE_AUD 0x0300
17 #define MUX_STAT_AUD 0x0400
18 #define MUX_IGNORE_AUD 0x0500
19 #define DIV_AUD0 0x0600
20 #define DIV_AUD1 0x0604
21 #define DIV_STAT_AUD0 0x0700
22 #define DIV_STAT_AUD1 0x0704
23 #define EN_ACLK_AUD 0x0800
24 #define EN_PCLK_AUD 0x0900
[all …]
/kernel/linux/linux-5.10/drivers/clk/samsung/
Dclk-exynos5260.h15 #define MUX_SEL_AUD 0x0200
16 #define MUX_ENABLE_AUD 0x0300
17 #define MUX_STAT_AUD 0x0400
18 #define MUX_IGNORE_AUD 0x0500
19 #define DIV_AUD0 0x0600
20 #define DIV_AUD1 0x0604
21 #define DIV_STAT_AUD0 0x0700
22 #define DIV_STAT_AUD1 0x0704
23 #define EN_ACLK_AUD 0x0800
24 #define EN_PCLK_AUD 0x0900
[all …]
/kernel/linux/linux-6.6/drivers/media/platform/qcom/venus/
Dhfi_venus_io.h9 #define VBIF_BASE 0x80000
11 #define VBIF_AXI_HALT_CTRL0 0x208
12 #define VBIF_AXI_HALT_CTRL1 0x20c
14 #define VBIF_AXI_HALT_CTRL0_HALT_REQ BIT(0)
15 #define VBIF_AXI_HALT_CTRL1_HALT_ACK BIT(0)
18 #define CPU_BASE 0xc0000
20 #define CPU_CS_BASE (CPU_BASE + 0x12000)
21 #define CPU_IC_BASE (CPU_BASE + 0x1f000)
22 #define CPU_BASE_V6 0xa0000
24 #define CPU_IC_BASE_V6 (CPU_BASE_V6 + 0x138)
[all …]
/kernel/linux/linux-5.10/drivers/media/platform/qcom/venus/
Dhfi_venus_io.h9 #define VBIF_BASE 0x80000
11 #define VBIF_AXI_HALT_CTRL0 0x208
12 #define VBIF_AXI_HALT_CTRL1 0x20c
14 #define VBIF_AXI_HALT_CTRL0_HALT_REQ BIT(0)
15 #define VBIF_AXI_HALT_CTRL1_HALT_ACK BIT(0)
18 #define CPU_BASE 0xc0000
20 #define CPU_CS_BASE (CPU_BASE + 0x12000)
21 #define CPU_IC_BASE (CPU_BASE + 0x1f000)
23 #define CPU_CS_A2HSOFTINTCLR 0x1c
25 #define VIDC_CTRL_INIT 0x48
[all …]
/kernel/linux/linux-5.10/arch/sh/include/mach-common/mach/
Durquell.h6 * ------ 0x00000000 ------------------------------------
8 * -----+ 0x04000000 ------------------------------------
10 * -----+ 0x08000000 ------------------------------------
13 * -----+ 0x10000000 ------------------------------------
15 * -----+ 0x14000000 ------------------------------------
17 * -----+ 0x18000000 ------------------------------------
19 * -----+ 0x1c000000 ------------------------------------
24 #define NOR_FLASH_ADDR 0x00000000
25 #define NOR_FLASH_SIZE 0x04000000
27 #define CS1_BASE 0x05000000
[all …]
/kernel/linux/linux-6.6/arch/sh/include/mach-common/mach/
Durquell.h6 * ------ 0x00000000 ------------------------------------
8 * -----+ 0x04000000 ------------------------------------
10 * -----+ 0x08000000 ------------------------------------
13 * -----+ 0x10000000 ------------------------------------
15 * -----+ 0x14000000 ------------------------------------
17 * -----+ 0x18000000 ------------------------------------
19 * -----+ 0x1c000000 ------------------------------------
24 #define NOR_FLASH_ADDR 0x00000000
25 #define NOR_FLASH_SIZE 0x04000000
27 #define CS1_BASE 0x05000000
[all …]
/kernel/linux/linux-6.6/include/uapi/linux/
Dmedia-bus-format.h16 * These bus formats uniquely identify data formats on the data bus. Format 0
35 #define MEDIA_BUS_FMT_FIXED 0x0001
37 /* RGB - next is 0x1025 */
38 #define MEDIA_BUS_FMT_RGB444_1X12 0x1016
39 #define MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE 0x1001
40 #define MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE 0x1002
41 #define MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE 0x1003
42 #define MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE 0x1004
43 #define MEDIA_BUS_FMT_RGB565_1X16 0x1017
44 #define MEDIA_BUS_FMT_BGR565_2X8_BE 0x1005
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/hisilicon/kirin/
Dkirin_ade_reg.h15 #define ADE_CTRL 0x0004
16 #define FRM_END_START_OFST 0
18 #define AUTO_CLK_GATE_EN_OFST 0
19 #define AUTO_CLK_GATE_EN BIT(0)
20 #define ADE_DISP_SRC_CFG 0x0018
21 #define ADE_CTRL1 0x008C
22 #define ADE_EN 0x0100
23 #define ADE_DISABLE 0
26 #define ADE_SOFT_RST_SEL(x) (0x0078 + (x) * 0x4)
27 #define ADE_RELOAD_DIS(x) (0x00AC + (x) * 0x4)
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/hisilicon/kirin/
Dkirin_ade_reg.h15 #define ADE_CTRL 0x0004
16 #define FRM_END_START_OFST 0
18 #define AUTO_CLK_GATE_EN_OFST 0
19 #define AUTO_CLK_GATE_EN BIT(0)
20 #define ADE_DISP_SRC_CFG 0x0018
21 #define ADE_CTRL1 0x008C
22 #define ADE_EN 0x0100
23 #define ADE_DISABLE 0
26 #define ADE_SOFT_RST_SEL(x) (0x0078 + (x) * 0x4)
27 #define ADE_RELOAD_DIS(x) (0x00AC + (x) * 0x4)
[all …]
/kernel/linux/linux-6.6/drivers/net/wireless/mediatek/mt76/mt76x2/
Dusb_mac.c11 s8 offset = 0; in mt76x2u_mac_fixup_xtal()
16 offset = eep_val & 0x7f; in mt76x2u_mac_fixup_xtal()
17 if ((eep_val & 0xff) == 0xff) in mt76x2u_mac_fixup_xtal()
18 offset = 0; in mt76x2u_mac_fixup_xtal()
19 else if (eep_val & 0x80) in mt76x2u_mac_fixup_xtal()
20 offset = 0 - offset; in mt76x2u_mac_fixup_xtal()
23 if (eep_val == 0x00 || eep_val == 0xff) { in mt76x2u_mac_fixup_xtal()
25 eep_val &= 0xff; in mt76x2u_mac_fixup_xtal()
27 if (eep_val == 0x00 || eep_val == 0xff) in mt76x2u_mac_fixup_xtal()
28 eep_val = 0x14; in mt76x2u_mac_fixup_xtal()
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/mediatek/mt76/mt76x2/
Dusb_mac.c11 s8 offset = 0; in mt76x2u_mac_fixup_xtal()
16 offset = eep_val & 0x7f; in mt76x2u_mac_fixup_xtal()
17 if ((eep_val & 0xff) == 0xff) in mt76x2u_mac_fixup_xtal()
18 offset = 0; in mt76x2u_mac_fixup_xtal()
19 else if (eep_val & 0x80) in mt76x2u_mac_fixup_xtal()
20 offset = 0 - offset; in mt76x2u_mac_fixup_xtal()
23 if (eep_val == 0x00 || eep_val == 0xff) { in mt76x2u_mac_fixup_xtal()
25 eep_val &= 0xff; in mt76x2u_mac_fixup_xtal()
27 if (eep_val == 0x00 || eep_val == 0xff) in mt76x2u_mac_fixup_xtal()
28 eep_val = 0x14; in mt76x2u_mac_fixup_xtal()
[all …]

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