Searched +full:0 +full:x10211000 (Results 1 – 19 of 19) sorted by relevance
19 #size-cells = <0>;21 cpu@0 {24 reg = <0x0>;29 reg = <0x1>;34 reg = <0x2>;39 reg = <0x3>;47 #clock-cells = <0>;53 #clock-cells = <0>;59 #clock-cells = <0>;65 reg = <0x10008000 0x80>;[all …]
19 #size-cells = <0>;21 cpu@0 {24 reg = <0x0>;29 reg = <0x1>;34 reg = <0x2>;39 reg = <0x3>;53 #clock-cells = <0>;59 #clock-cells = <0>;65 #clock-cells = <0>;77 reg = <0x10008000 0x80>;[all …]
19 #size-cells = <0>;21 cpu@0 {24 reg = <0x0>;29 reg = <0x1>;34 reg = <0x2>;39 reg = <0x3>;44 reg = <0x4>;49 reg = <0x5>;54 reg = <0x6>;59 reg = <0x7>;[all …]
19 #size-cells = <0>;22 cpu@0 {25 reg = <0x0>;30 reg = <0x1>;35 reg = <0x2>;40 reg = <0x3>;52 reg = <0 0x80002000 0 0x1000>;65 #clock-cells = <0>;71 #clock-cells = <0>;77 #clock-cells = <0>;[all …]
42 #size-cells = <0>;45 cpu0: cpu@0 {48 reg = <0x000>;54 reg = <0x001>;60 reg = <0x100>;66 reg = <0x101>;77 reg = <0 0x80002000 0 0x1000>;90 #clock-cells = <0>;96 #clock-cells = <0>;101 #clock-cells = <0>;[all …]
25 #size-cells = <0>;28 cpu@0 {31 reg = <0x0>;36 reg = <0x1>;41 reg = <0x2>;46 reg = <0x3>;57 reg = <0 0x80002000 0 0x1000>;64 #clock-cells = <0>;70 #clock-cells = <0>;73 clk26m: oscillator@0 {[all …]
73 #size-cells = <0>;76 cpu0: cpu@0 {79 reg = <0x0>;91 reg = <0x1>;103 reg = <0x2>;115 reg = <0x3>;137 #clock-cells = <0>;142 #clock-cells = <0>;147 clk26m: oscillator-0 {149 #clock-cells = <0>;[all …]
17 #size-cells = <0>;19 cpu@0 {22 reg = <0x0>;27 reg = <0x1>;32 reg = <0x2>;37 reg = <0x3>;44 #clock-cells = <0>;50 #clock-cells = <0>;56 #clock-cells = <0>;61 reg = <0x10008000 0x80>;[all …]
19 #size-cells = <0>;22 cpu@0 {25 reg = <0x0>;30 reg = <0x1>;35 reg = <0x2>;40 reg = <0x3>;54 #clock-cells = <0>;60 #clock-cells = <0>;66 #clock-cells = <0>;78 reg = <0x10008000 0x80>;[all …]
315 enum: [0, 1]321 are from 0 to 15.328 from 0 to 63.347 reg = <0 0x10211000 0 0x1000>;
65 Valid arguments for 'slew-rate' are '0' for no slew rate controlled and '1' for74 cycle when asserted (high pulse width adjustment). Valid arguments are from 077 cycle when asserted (high pulse width adjustment). Valid arguments are from 090 PIN 0: "GPIO_A"333 PIN 0: "TOP_5G_CLK"455 "wf0_5g" "wifi" 0, 1, 2, 3, 4, 5, 6,462 reg = <0 0x10211000 0 0x1000>;
69 #size-cells = <0>;71 cpu0: cpu@0 {74 reg = <0x0 0x0>;88 reg = <0x0 0x1>;103 #clock-cells = <0>;108 #clock-cells = <0>;132 reg = <0 0x43000000 0 0x30000>;142 thermal-sensors = <&thermal 0>;208 reg = <0 0x10000000 0 0x1000>;215 reg = <0 0x10001000 0 0x250>;[all …]
69 #size-cells = <0>;71 cpu0: cpu@0 {74 reg = <0x0 0x0>;89 reg = <0x0 0x1>;111 #clock-cells = <0>;116 #clock-cells = <0>;140 reg = <0 0x43000000 0 0x30000>;150 thermal-sensors = <&thermal 0>;216 reg = <0 0x10000000 0 0x1000>;223 reg = <0 0x10001000 0 0x250>;[all …]