Searched +full:0 +full:x15000000 (Results 1 – 25 of 93) sorted by relevance
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| /kernel/linux/linux-5.10/arch/sh/boards/mach-hp6xx/ |
| D | setup.c | 21 #define SCPCR 0xa4000116
22 #define SCPDR 0xa4000136
26 [0] = {
27 .start = 0x15000000 + 0x1f0,
28 .end = 0x15000000 + 0x1f0 + 0x08 - 0x01,
32 .start = 0x15000000 + 0x1fe,
33 .end = 0x15000000 + 0x1fe + 0x01,
37 .start = evt2irq(0xba0),
87 sh_dac_output(0, pdata->channel); in dac_audio_stop()
149 sh_dac_output(0, DAC_SPEAKER_VOLUME); in hp6xx_setup()
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| /kernel/linux/linux-6.6/arch/sh/boards/mach-hp6xx/ |
| D | setup.c | 21 #define SCPCR 0xa4000116
22 #define SCPDR 0xa4000136
26 [0] = {
27 .start = 0x15000000 + 0x1f0,
28 .end = 0x15000000 + 0x1f0 + 0x08 - 0x01,
32 .start = 0x15000000 + 0x1fe,
33 .end = 0x15000000 + 0x1fe + 0x01,
37 .start = evt2irq(0xba0),
87 sh_dac_output(0, pdata->channel); in dac_audio_stop()
149 sh_dac_output(0, DAC_SPEAKER_VOLUME); in hp6xx_setup()
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| /kernel/linux/linux-5.10/arch/mips/vr41xx/ibm-workpad/ |
| D | setup.c | 12 #define WORKPAD_ISA_IO_BASE 0x15000000
13 #define WORKPAD_ISA_IO_SIZE 0x03000000
14 #define WORKPAD_ISA_IO_START 0
24 return 0; in ibm_workpad_setup()
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/arm/mediatek/ |
| D | mediatek,imgsys.txt | 28 reg = <0 0x15000000 0 0x1000>;
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| D | mediatek,mt8195-clock.yaml | 68 reg = <0x10720000 0x1000>;
75 reg = <0x11d03000 0x1000>;
82 reg = <0x11e05000 0x1000>;
89 reg = <0x13fbf000 0x1000>;
96 reg = <0x14e00000 0x1000>;
103 reg = <0x14e02000 0x1000>;
110 reg = <0x14e03000 0x1000>;
117 reg = <0x15000000 0x1000>;
124 reg = <0x15110000 0x1000>;
131 reg = <0x15130000 0x1000>;
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/mediatek/ |
| D | mediatek,imgsys.txt | 28 reg = <0 0x15000000 0 0x1000>;
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | integrator.dtsi | 12 reg = <0x0 0x0>;
17 reg = <0x10000000 0x200>;
20 led@c.0 {
22 offset = <0x0c>;
23 mask = <0x01>;
32 reg = <0x12000000 0x100>;
36 reg = <0x13000000 0x100>;
42 reg = <0x13000100 0x100>;
48 reg = <0x13000200 0x100>;
57 reg = <0x14000000 0x100>;
[all …]
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| D | omap3-lilly-dbb056.dts | 25 pinctrl-0 = <&lcd_pins>;
29 OMAP3_CORE1_IOPAD(0x2114, PIN_INPUT | MUX_MODE4) /* cam_fld.gpio_98 */
35 OMAP3_CORE1_IOPAD(0x212e, PIN_INPUT | MUX_MODE4) /* cam_xclkb.gpio_111 -> sja1000 IRQ */
41 …OMAP3_CORE1_IOPAD(0x218c, PIN_OUTPUT | PIN_OFF_OUTPUT_HIGH | MUX_MODE4) /* mcbsp1_clk.gpio_156 -…
47 OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
48 OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
49 OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */
50 OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */
51 OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */
52 OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */
[all …]
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| D | imx1.dtsi | 38 reg = <0x00223000 0x1000>;
42 #size-cells = <0>;
45 cpu@0 {
47 reg = <0>;
59 #clock-cells = <0>;
75 reg = <0x00200000 0x10000>;
80 reg = <0x00202000 0x1000>;
89 reg = <0x00203000 0x1000>;
98 reg = <0x00205000 0x1000>;
109 reg = <0x00206000 0x1000>;
[all …]
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| D | mt7623n.dtsi | 22 reg = <0 0x13000000 0 0x200>;
29 reg = <0 0x13040000 0 0x30000>;
55 reg = <0 0x14000000 0 0x1000>;
62 reg = <0 0x14010000 0 0x1000>;
64 mediatek,larb-id = <0>;
74 reg = <0 0x16010000 0 0x1000>;
86 reg = <0 0x15001000 0 0x1000>;
99 reg = <0 0x15000000 0 0x1000>;
106 reg = <0 0x10205000 0 0x1000>;
117 reg = <0 0x15004000 0 0x1000>;
[all …]
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| /kernel/linux/linux-6.6/arch/arm/boot/dts/arm/ |
| D | integrator.dtsi | 12 reg = <0x0 0x0>;
17 reg = <0x10000000 0x200>;
18 ranges = <0x0 0x10000000 0x200>;
23 led@c,0 {
25 reg = <0x0c 0x04>;
26 offset = <0x0c>;
27 mask = <0x01>;
36 reg = <0x12000000 0x100>;
40 reg = <0x13000000 0x100>;
46 reg = <0x13000100 0x100>;
[all …]
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| /kernel/linux/linux-5.10/arch/sh/include/mach-common/mach/ |
| D | urquell.h | 6 * ------ 0x00000000 ------------------------------------
8 * -----+ 0x04000000 ------------------------------------
10 * -----+ 0x08000000 ------------------------------------
13 * -----+ 0x10000000 ------------------------------------
15 * -----+ 0x14000000 ------------------------------------
17 * -----+ 0x18000000 ------------------------------------
19 * -----+ 0x1c000000 ------------------------------------
24 #define NOR_FLASH_ADDR 0x00000000
25 #define NOR_FLASH_SIZE 0x04000000
27 #define CS1_BASE 0x05000000
[all …]
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| /kernel/linux/linux-6.6/arch/sh/include/mach-common/mach/ |
| D | urquell.h | 6 * ------ 0x00000000 ------------------------------------
8 * -----+ 0x04000000 ------------------------------------
10 * -----+ 0x08000000 ------------------------------------
13 * -----+ 0x10000000 ------------------------------------
15 * -----+ 0x14000000 ------------------------------------
17 * -----+ 0x18000000 ------------------------------------
19 * -----+ 0x1c000000 ------------------------------------
24 #define NOR_FLASH_ADDR 0x00000000
25 #define NOR_FLASH_SIZE 0x04000000
27 #define CS1_BASE 0x05000000
[all …]
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/mediatek/ |
| D | mt8167.dtsi | 22 reg = <0 0x10000000 0 0x1000>;
28 reg = <0 0x10001000 0 0x1000>;
34 reg = <0 0x10018000 0 0x710>;
40 reg = <0 0x10006000 0 0x1000>;
45 #size-cells = <0>;
53 #power-domain-cells = <0>;
62 #power-domain-cells = <0>;
69 #power-domain-cells = <0>;
78 #size-cells = <0>;
85 #size-cells = <0>;
[all …]
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| /kernel/linux/linux-6.6/arch/sh/boards/ |
| D | board-urquell.c | 32 * SW2 0x1x xxxx -> little endian
39 * 0x00000000 - 0x04000000 (CS0) Nor Flash
40 * 0x04000000 - 0x04200000 (CS1) SRAM
41 * 0x05000000 - 0x05800000 (CS1) on board register
42 * 0x05800000 - 0x06000000 (CS1) LAN91C111
43 * 0x06000000 - 0x06400000 (CS1) PCMCIA
44 * 0x08000000 - 0x10000000 (CS2-CS3) DDR3
45 * 0x10000000 - 0x14000000 (CS4) PCIe
46 * 0x14000000 - 0x14800000 (CS5) Core0 LRAM/URAM
47 * 0x14800000 - 0x15000000 (CS5) Core1 LRAM/URAM
[all …]
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| /kernel/linux/linux-5.10/arch/sh/boards/ |
| D | board-urquell.c | 32 * SW2 0x1x xxxx -> little endian
39 * 0x00000000 - 0x04000000 (CS0) Nor Flash
40 * 0x04000000 - 0x04200000 (CS1) SRAM
41 * 0x05000000 - 0x05800000 (CS1) on board register
42 * 0x05800000 - 0x06000000 (CS1) LAN91C111
43 * 0x06000000 - 0x06400000 (CS1) PCMCIA
44 * 0x08000000 - 0x10000000 (CS2-CS3) DDR3
45 * 0x10000000 - 0x14000000 (CS4) PCIe
46 * 0x14000000 - 0x14800000 (CS5) Core0 LRAM/URAM
47 * 0x14800000 - 0x15000000 (CS5) Core1 LRAM/URAM
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/nbio/ |
| D | nbio_7_0_default.h | 26 #define cfgNB_NBCFG0_NB_VENDOR_ID_DEFAULT 0x00000000
27 #define cfgNB_NBCFG0_NB_DEVICE_ID_DEFAULT 0x00000000
28 #define cfgNB_NBCFG0_NB_COMMAND_DEFAULT 0x00000000
29 #define cfgNB_NBCFG0_NB_STATUS_DEFAULT 0x00000000
30 #define cfgNB_NBCFG0_NB_REVISION_ID_DEFAULT 0x00000000
31 #define cfgNB_NBCFG0_NB_REGPROG_INF_DEFAULT 0x00000000
32 #define cfgNB_NBCFG0_NB_SUB_CLASS_DEFAULT 0x00000000
33 #define cfgNB_NBCFG0_NB_BASE_CODE_DEFAULT 0x00000000
34 #define cfgNB_NBCFG0_NB_CACHE_LINE_DEFAULT 0x00000000
35 #define cfgNB_NBCFG0_NB_LATENCY_DEFAULT 0x00000000
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/nbio/ |
| D | nbio_7_0_default.h | 26 #define cfgNB_NBCFG0_NB_VENDOR_ID_DEFAULT 0x00000000
27 #define cfgNB_NBCFG0_NB_DEVICE_ID_DEFAULT 0x00000000
28 #define cfgNB_NBCFG0_NB_COMMAND_DEFAULT 0x00000000
29 #define cfgNB_NBCFG0_NB_STATUS_DEFAULT 0x00000000
30 #define cfgNB_NBCFG0_NB_REVISION_ID_DEFAULT 0x00000000
31 #define cfgNB_NBCFG0_NB_REGPROG_INF_DEFAULT 0x00000000
32 #define cfgNB_NBCFG0_NB_SUB_CLASS_DEFAULT 0x00000000
33 #define cfgNB_NBCFG0_NB_BASE_CODE_DEFAULT 0x00000000
34 #define cfgNB_NBCFG0_NB_CACHE_LINE_DEFAULT 0x00000000
35 #define cfgNB_NBCFG0_NB_LATENCY_DEFAULT 0x00000000
[all …]
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| /kernel/linux/linux-6.6/arch/arm/boot/dts/ti/omap/ |
| D | omap3-lilly-dbb056.dts | 25 pinctrl-0 = <&lcd_pins>;
29 OMAP3_CORE1_IOPAD(0x2114, PIN_INPUT | MUX_MODE4) /* cam_fld.gpio_98 */
35 OMAP3_CORE1_IOPAD(0x212e, PIN_INPUT | MUX_MODE4) /* cam_xclkb.gpio_111 -> sja1000 IRQ */
41 …OMAP3_CORE1_IOPAD(0x218c, PIN_OUTPUT | PIN_OFF_OUTPUT_HIGH | MUX_MODE4) /* mcbsp1_clk.gpio_156 -…
47 OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
48 OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
49 OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */
50 OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */
51 OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */
52 OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */
[all …]
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| /kernel/linux/linux-5.10/arch/mips/include/asm/txx9/ |
| D | jmr3927.h | 18 #define JMR3927_ROMCE0 0x1fc00000 /* 4M */
19 #define JMR3927_ROMCE1 0x1e000000 /* 4M */
20 #define JMR3927_ROMCE2 0x14000000 /* 16M */
21 #define JMR3927_ROMCE3 0x10000000 /* 64M */
22 #define JMR3927_ROMCE5 0x1d000000 /* 4M */
23 #define JMR3927_SDCS0 0x00000000 /* 32M */
24 #define JMR3927_SDCS1 0x02000000 /* 32M */
27 #define JMR3927_PCIMEM 0x08000000
28 #define JMR3927_PCIMEM_SIZE 0x08000000 /* 128M */
29 #define JMR3927_PCIIO 0x15000000
[all …]
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| /kernel/linux/linux-6.6/arch/arm/mach-versatile/ |
| D | integrator-hardware.h | 14 #define IO_BASE 0xF0000000 // VA of IO
15 #define IO_SIZE 0x0B000000 // How much?
19 #define IO_ADDRESS(x) (((x) & 0x000fffff) | (((x) >> 4) & 0x0ff00000) | IO_BASE)
25 #define INTEGRATOR_BOOT_ROM_LO 0x00000000
26 #define INTEGRATOR_BOOT_ROM_HI 0x20000000
40 #define INTEGRATOR_SSRAM_BASE 0x00000000
41 #define INTEGRATOR_SSRAM_ALIAS_BASE 0x10800000
44 #define INTEGRATOR_FLASH_BASE 0x24000000
47 #define INTEGRATOR_MBRD_SSRAM_BASE 0x28000000
53 #define INTEGRATOR_SDRAM_BASE 0x00040000
[all …]
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| /kernel/linux/linux-6.6/arch/arm/boot/dts/nxp/imx/ |
| D | imx1.dtsi | 38 reg = <0x00223000 0x1000>;
42 #size-cells = <0>;
45 cpu@0 {
47 reg = <0>;
59 #clock-cells = <0>;
75 reg = <0x00200000 0x10000>;
80 reg = <0x00202000 0x1000>;
89 reg = <0x00203000 0x1000>;
98 reg = <0x00205000 0x1000>;
109 reg = <0x00206000 0x1000>;
[all …]
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| /kernel/linux/linux-5.10/arch/arm/mach-integrator/ |
| D | hardware.h | 14 #define IO_BASE 0xF0000000 // VA of IO
15 #define IO_SIZE 0x0B000000 // How much?
20 #define IO_ADDRESS(x) (((x) & 0x000fffff) | (((x) >> 4) & 0x0ff00000) | IO_BASE)
30 #define INTEGRATOR_BOOT_ROM_LO 0x00000000
31 #define INTEGRATOR_BOOT_ROM_HI 0x20000000
45 #define INTEGRATOR_SSRAM_BASE 0x00000000
46 #define INTEGRATOR_SSRAM_ALIAS_BASE 0x10800000
49 #define INTEGRATOR_FLASH_BASE 0x24000000
52 #define INTEGRATOR_MBRD_SSRAM_BASE 0x28000000
58 #define INTEGRATOR_SDRAM_BASE 0x00040000
[all …]
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| /kernel/linux/linux-6.6/arch/arm/boot/dts/mediatek/ |
| D | mt7623n.dtsi | 22 reg = <0 0x13000000 0 0x200>;
29 reg = <0 0x13040000 0 0x30000>;
55 reg = <0 0x14000000 0 0x1000>;
62 reg = <0 0x14010000 0 0x1000>;
64 mediatek,larb-id = <0>;
74 reg = <0 0x16010000 0 0x1000>;
86 reg = <0 0x15001000 0 0x1000>;
99 reg = <0 0x15000000 0 0x1000>;
106 reg = <0 0x10205000 0 0x1000>;
117 reg = <0 0x15004000 0 0x1000>;
[all …]
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| /kernel/linux/linux-6.6/fs/freevxfs/ |
| D | vxfs.h | 20 #define VXFS_SUPER_MAGIC 0xa501FCF5
176 * File modes. File types above 0xf000 are vxfs internal only, they should
181 VXFS_ISUID = 0x00000800, /* setuid */
182 VXFS_ISGID = 0x00000400, /* setgid */
183 VXFS_ISVTX = 0x00000200, /* sticky bit */
184 VXFS_IREAD = 0x00000100, /* read */
185 VXFS_IWRITE = 0x00000080, /* write */
186 VXFS_IEXEC = 0x00000040, /* exec */
188 VXFS_IFIFO = 0x00001000, /* Named pipe */
189 VXFS_IFCHR = 0x00002000, /* Character device */
[all …]
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