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/kernel/linux/linux-5.10/drivers/memory/tegra/
Dtegra30.c36 .id = 0x00,
40 .id = 0x01,
44 .reg = 0x228,
48 .reg = 0x2e8,
49 .shift = 0,
50 .mask = 0xff,
51 .def = 0x4e,
54 .id = 0x02,
58 .reg = 0x228,
62 .reg = 0x2f4,
[all …]
Dtegra114.c15 .id = 0x00,
19 .id = 0x01,
23 .reg = 0x228,
27 .reg = 0x2e8,
28 .shift = 0,
29 .mask = 0xff,
30 .def = 0x4e,
33 .id = 0x02,
37 .reg = 0x228,
41 .reg = 0x2f4,
[all …]
Dtegra124.c15 .id = 0x00,
19 .id = 0x01,
23 .reg = 0x228,
27 .reg = 0x2e8,
28 .shift = 0,
29 .mask = 0xff,
30 .def = 0xc2,
33 .id = 0x02,
37 .reg = 0x228,
41 .reg = 0x2f4,
[all …]
Dtegra210.c12 .id = 0x00,
16 .id = 0x01,
20 .reg = 0x228,
24 .reg = 0x2e8,
25 .shift = 0,
26 .mask = 0xff,
27 .def = 0xc2,
30 .id = 0x02,
34 .reg = 0x228,
38 .reg = 0x2f4,
[all …]
/kernel/linux/linux-6.6/drivers/memory/tegra/
Dtegra30.c37 .id = 0x00,
42 .reg = 0x34c,
43 .shift = 0,
44 .mask = 0xff,
45 .def = 0x0,
50 .id = 0x01,
55 .reg = 0x228,
59 .reg = 0x2e8,
60 .shift = 0,
61 .mask = 0xff,
[all …]
Dtegra114.c15 .id = 0x00,
20 .reg = 0x34c,
21 .shift = 0,
22 .mask = 0xff,
23 .def = 0x0,
27 .id = 0x01,
32 .reg = 0x228,
36 .reg = 0x2e8,
37 .shift = 0,
38 .mask = 0xff,
[all …]
Dtegra210.c12 .id = 0x00,
16 .id = 0x01,
21 .reg = 0x228,
25 .reg = 0x2e8,
26 .shift = 0,
27 .mask = 0xff,
28 .def = 0x1e,
32 .id = 0x02,
37 .reg = 0x228,
41 .reg = 0x2f4,
[all …]
Dtegra124.c16 .id = 0x00,
21 .reg = 0x34c,
22 .shift = 0,
23 .mask = 0xff,
24 .def = 0x0,
28 .id = 0x01,
33 .reg = 0x228,
37 .reg = 0x2e8,
38 .shift = 0,
39 .mask = 0xff,
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pinctrl/
Dfsl,imx8mp-pinctrl.yaml72 reg = <0x30330000 0x10000>;
76 <0x228 0x488 0x5F0 0x0 0x6 0x49>,
77 <0x228 0x488 0x000 0x0 0x0 0x49>;
/kernel/linux/linux-6.6/include/linux/soc/mediatek/
Dinfracfg.h5 #define MT8195_TOP_AXI_PROT_EN_STA1 0x228
6 #define MT8195_TOP_AXI_PROT_EN_1_STA1 0x258
7 #define MT8195_TOP_AXI_PROT_EN_SET 0x2a0
8 #define MT8195_TOP_AXI_PROT_EN_CLR 0x2a4
9 #define MT8195_TOP_AXI_PROT_EN_1_SET 0x2a8
10 #define MT8195_TOP_AXI_PROT_EN_1_CLR 0x2ac
11 #define MT8195_TOP_AXI_PROT_EN_MM_SET 0x2d4
12 #define MT8195_TOP_AXI_PROT_EN_MM_CLR 0x2d8
13 #define MT8195_TOP_AXI_PROT_EN_MM_STA1 0x2ec
14 #define MT8195_TOP_AXI_PROT_EN_2_SET 0x714
[all …]
/kernel/linux/linux-5.10/include/dt-bindings/clock/
Dam4.h8 #define AM4_CLKCTRL_OFFSET 0x20
14 #define AM4_ADC_TSC_CLKCTRL AM4_CLKCTRL_INDEX(0x120)
15 #define AM4_L4_WKUP_CLKCTRL AM4_CLKCTRL_INDEX(0x220)
16 #define AM4_WKUP_M3_CLKCTRL AM4_CLKCTRL_INDEX(0x228)
17 #define AM4_COUNTER_32K_CLKCTRL AM4_CLKCTRL_INDEX(0x230)
18 #define AM4_TIMER1_CLKCTRL AM4_CLKCTRL_INDEX(0x328)
19 #define AM4_WD_TIMER2_CLKCTRL AM4_CLKCTRL_INDEX(0x338)
20 #define AM4_I2C1_CLKCTRL AM4_CLKCTRL_INDEX(0x340)
21 #define AM4_UART1_CLKCTRL AM4_CLKCTRL_INDEX(0x348)
22 #define AM4_SMARTREFLEX0_CLKCTRL AM4_CLKCTRL_INDEX(0x350)
[all …]
/kernel/linux/linux-6.6/include/dt-bindings/clock/
Dam4.h8 #define AM4_CLKCTRL_OFFSET 0x20
12 #define AM4_L3S_TSC_CLKCTRL_OFFSET 0x120
14 #define AM4_L3S_TSC_ADC_TSC_CLKCTRL AM4_L3S_TSC_CLKCTRL_INDEX(0x120)
17 #define AM4_L4_WKUP_AON_CLKCTRL_OFFSET 0x228
19 #define AM4_L4_WKUP_AON_WKUP_M3_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x228)
20 #define AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x230)
23 #define AM4_L4_WKUP_CLKCTRL_OFFSET 0x220
25 #define AM4_L4_WKUP_L4_WKUP_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x220)
26 #define AM4_L4_WKUP_TIMER1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x328)
27 #define AM4_L4_WKUP_WD_TIMER2_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x338)
[all …]
/kernel/linux/linux-6.6/arch/arm/mm/
Dcache-tauros3.h20 #define TAUROS3_EVENT_CNT2_CFG 0x224
21 #define TAUROS3_EVENT_CNT2_VAL 0x228
22 #define TAUROS3_INV_ALL 0x780
23 #define TAUROS3_CLEAN_ALL 0x784
24 #define TAUROS3_AUX2_CTRL 0x820
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/arm/altera/
Dsocfpga-system.txt11 reg = <0xffd08000 0x1000>;
12 cpu1-start-addr = <0xffd080c4>;
24 reg = <0xffd12000 0x228>;
/kernel/linux/linux-5.10/arch/arm/mm/
Dcache-tauros3.h20 #define TAUROS3_EVENT_CNT2_CFG 0x224
21 #define TAUROS3_EVENT_CNT2_VAL 0x228
22 #define TAUROS3_INV_ALL 0x780
23 #define TAUROS3_CLEAN_ALL 0x784
24 #define TAUROS3_AUX2_CTRL 0x820
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/altera/
Dsocfpga-system.txt11 reg = <0xffd08000 0x1000>;
12 cpu1-start-addr = <0xffd080c4>;
24 reg = <0xffd12000 0x228>;
/kernel/linux/linux-6.6/drivers/phy/qualcomm/
Dphy-qcom-qmp-qserdes-txrx-v6_20.h9 #define QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_TX 0x30
10 #define QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_RX 0x34
11 #define QSERDES_V6_20_TX_TRAN_DRVR_EMP_EN 0xac
12 #define QSERDES_V6_20_TX_LANE_MODE_1 0x78
13 #define QSERDES_V6_20_TX_LANE_MODE_2 0x7c
14 #define QSERDES_V6_20_TX_LANE_MODE_3 0x80
16 #define QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2 0x08
17 #define QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3 0x0c
18 #define QSERDES_V6_20_RX_UCDR_PI_CONTROLS 0x20
19 #define QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3 0x34
[all …]
/kernel/linux/linux-6.6/drivers/mfd/
Ddb8500-prcmu-regs.h17 #define PRCM_ACLK_MGT (0x004)
18 #define PRCM_SVAMMCSPCLK_MGT (0x008)
19 #define PRCM_SIAMMDSPCLK_MGT (0x00C)
20 #define PRCM_SGACLK_MGT (0x014)
21 #define PRCM_UARTCLK_MGT (0x018)
22 #define PRCM_MSP02CLK_MGT (0x01C)
23 #define PRCM_I2CCLK_MGT (0x020)
24 #define PRCM_SDMMCCLK_MGT (0x024)
25 #define PRCM_SLIMCLK_MGT (0x028)
26 #define PRCM_PER1CLK_MGT (0x02C)
[all …]
/kernel/linux/linux-5.10/drivers/mfd/
Ddbx500-prcmu-regs.h17 #define PRCM_ACLK_MGT (0x004)
18 #define PRCM_SVAMMCSPCLK_MGT (0x008)
19 #define PRCM_SIAMMDSPCLK_MGT (0x00C)
20 #define PRCM_SGACLK_MGT (0x014)
21 #define PRCM_UARTCLK_MGT (0x018)
22 #define PRCM_MSP02CLK_MGT (0x01C)
23 #define PRCM_I2CCLK_MGT (0x020)
24 #define PRCM_SDMMCCLK_MGT (0x024)
25 #define PRCM_SLIMCLK_MGT (0x028)
26 #define PRCM_PER1CLK_MGT (0x02C)
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/remoteproc/
Dst-rproc.txt29 reg = <0x42000000 0x01000000>;
40 st,syscfg = <&syscfg_core 0x228>;
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/remoteproc/
Dst-rproc.txt29 reg = <0x42000000 0x01000000>;
40 st,syscfg = <&syscfg_core 0x228>;
/kernel/linux/linux-6.6/drivers/net/ethernet/sunplus/
Dspl2sw_register.h10 #define L2SW_SW_INT_STATUS_0 0x0
11 #define L2SW_SW_INT_MASK_0 0x4
12 #define L2SW_FL_CNTL_TH 0x8
13 #define L2SW_CPU_FL_CNTL_TH 0xc
14 #define L2SW_PRI_FL_CNTL 0x10
15 #define L2SW_VLAN_PRI_TH 0x14
16 #define L2SW_EN_TOS_BUS 0x18
17 #define L2SW_TOS_MAP0 0x1c
18 #define L2SW_TOS_MAP1 0x20
19 #define L2SW_TOS_MAP2 0x24
[all …]
/kernel/linux/linux-6.6/Documentation/bpf/
Dclassic_vs_extended.rst155 sub $0x228,%rsp
156 mov %rbx,-0x228(%rbp)
157 mov %r13,-0x220(%rbp)
159 mov $0x2,%esi
160 mov $0x3,%edx
161 mov $0x4,%ecx
162 mov $0x5,%r8d
166 mov $0x6,%esi
167 mov $0x7,%edx
168 mov $0x8,%ecx
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/marvell/octeontx2/nic/
Dotx2_reg.h17 #define RVU_PF_VFX_PFVF_MBOX0 (0x00000)
18 #define RVU_PF_VFX_PFVF_MBOX1 (0x00008)
19 #define RVU_PF_VFX_PFVF_MBOXX(a, b) (0x0 | (a) << 12 | (b) << 3)
20 #define RVU_PF_VF_BAR4_ADDR (0x10)
21 #define RVU_PF_BLOCK_ADDRX_DISC(a) (0x200 | (a) << 3)
22 #define RVU_PF_VFME_STATUSX(a) (0x800 | (a) << 3)
23 #define RVU_PF_VFTRPENDX(a) (0x820 | (a) << 3)
24 #define RVU_PF_VFTRPEND_W1SX(a) (0x840 | (a) << 3)
25 #define RVU_PF_VFPF_MBOX_INTX(a) (0x880 | (a) << 3)
26 #define RVU_PF_VFPF_MBOX_INT_W1SX(a) (0x8A0 | (a) << 3)
[all …]
/kernel/linux/linux-6.6/drivers/clk/meson/
Daxg.h19 #define HHI_GP0_PLL_CNTL 0x40
20 #define HHI_GP0_PLL_CNTL2 0x44
21 #define HHI_GP0_PLL_CNTL3 0x48
22 #define HHI_GP0_PLL_CNTL4 0x4c
23 #define HHI_GP0_PLL_CNTL5 0x50
24 #define HHI_GP0_PLL_STS 0x54
25 #define HHI_GP0_PLL_CNTL1 0x58
26 #define HHI_HIFI_PLL_CNTL 0x80
27 #define HHI_HIFI_PLL_CNTL2 0x84
28 #define HHI_HIFI_PLL_CNTL3 0x88
[all …]

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