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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/
Dqcom,msm8996-qmp-pcie-phy.yaml57 "^phy@[0-9a-f]+$":
92 const: 0
98 const: 0
130 reg = <0x34000 0x488>;
133 ranges = <0x0 0x34000 0x4000>;
149 reg = <0x1000 0x130>,
150 <0x1200 0x200>,
151 <0x1400 0x1dc>;
156 #clock-cells = <0>;
159 #phy-cells = <0>;
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/ti/omap/
Dam57-pruss.dtsi11 reg = <0x4b226000 0x4>,
12 <0x4b226004 0x4>;
23 clocks = <&l4per2_clkctrl DRA7_L4PER2_PRUSS1_CLKCTRL 0>;
27 ranges = <0x00000000 0x4b200000 0x80000>;
29 pruss1: pruss@0 {
31 reg = <0x0 0x80000>;
36 pruss1_mem: memories@0 {
37 reg = <0x0 0x2000>,
38 <0x2000 0x2000>,
39 <0x10000 0x8000>;
[all …]
/kernel/linux/linux-6.6/include/linux/mfd/
Drsmu.h16 RSMU_CM = 0x34000,
17 RSMU_SABRE = 0x33810,
18 RSMU_SL = 0x19850,
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/remoteproc/
Dti,pru-rproc.yaml19 The K3 SoCs containing ICSSG v1.0 (eg: AM65x SR1.0) also have two Auxiliary
21 containing the revised ICSSG v1.1 (eg: J721E, AM65x SR2.0) have an extra two
46 - ti,am654-tx-pru # for Tx_PRUs in K3 AM65x SR2.0 SoCs
79 pattern: "^rtu@[0-9a-f]+$"
91 pattern: "^txpru@[0-9a-f]+"
95 pattern: "^pru@[0-9a-f]+$"
108 pruss_tm: target-module@300000 { /* 0x4a300000, ap 9 04.0 */
112 ranges = <0x0 0x300000 0x80000>;
114 pruss: pruss@0 {
116 reg = <0x0 0x80000>;
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/dma/
Dapple,admac.yaml51 an empty phandle reference <0>.
84 reg = <0x38200000 0x34000>;
86 interrupts-extended = <0>,
88 <0>,
89 <0>;
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/disp/mdp5/
Dmdp5_cfg.c22 0,
35 .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
36 .flush_hw_mask = 0x0003ffff,
40 .base = { 0x01100, 0x01500, 0x01900 },
45 0,
49 .base = { 0x01d00, 0x02100, 0x02500 },
53 0,
57 .base = { 0x02900, 0x02d00 },
60 0,
64 .base = { 0x03100, 0x03500, 0x03900, 0x03d00, 0x04100 },
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/disp/mdp5/
Dmdp5_cfg.c22 0,
35 .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
36 .flush_hw_mask = 0x0003ffff,
40 .base = { 0x01100, 0x01500, 0x01900 },
45 0,
49 .base = { 0x01d00, 0x02100, 0x02500 },
53 0,
57 .base = { 0x02900, 0x02d00 },
60 0,
64 .base = { 0x03100, 0x03500, 0x03900, 0x03d00, 0x04100 },
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-mv78xx0/
Dmv78xx0.h20 * f0800000 PCIe #0 I/O space
32 * fee00000 f0800000 64K PCIe #0 I/O space
42 #define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000
43 #define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000
44 #define MV78XX0_CORE_REGS_VIRT_BASE IOMEM(0xfe400000)
45 #define MV78XX0_CORE_REGS_PHYS_BASE 0xfe400000
48 #define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20))
51 #define MV78XX0_REGS_PHYS_BASE 0xf1000000
52 #define MV78XX0_REGS_VIRT_BASE IOMEM(0xfec00000)
55 #define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000
[all …]
/kernel/linux/linux-6.6/arch/arm/mach-mv78xx0/
Dmv78xx0.h17 * f0800000 PCIe #0 I/O space
29 * fee00000 f0800000 64K PCIe #0 I/O space
39 #define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000
40 #define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000
41 #define MV78XX0_CORE_REGS_VIRT_BASE IOMEM(0xfe400000)
42 #define MV78XX0_CORE_REGS_PHYS_BASE 0xfe400000
45 #define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20))
48 #define MV78XX0_REGS_PHYS_BASE 0xf1000000
49 #define MV78XX0_REGS_VIRT_BASE IOMEM(0xfec00000)
52 #define MV78XX0_SRAM_PHYS_BASE (0xf2200000)
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/soc/ti/
Dti,pruss.yaml36 0x0, but also has access to a secondary Data RAM (primary to the other PRU
37 core) at its address 0x2000. A shared Data RAM, if present, can be accessed
60 pattern: "^(pruss|icssg)@[0-9a-f]+$"
65 - ti,am4376-pruss0 # for AM437x SoC family and PRUSS unit 0
161 const: 0
175 const: 0
209 const: 0
297 "^(pru|rtu|txpru)@[0-9a-f]+$":
350 pruss: pruss@0 {
352 reg = <0x0 0x80000>;
[all …]
/kernel/linux/linux-5.10/arch/powerpc/boot/dts/fsl/
Db4si-post.dtsi37 alloc-ranges = <0 0 0x10000 0>;
42 alloc-ranges = <0 0 0x10000 0>;
47 alloc-ranges = <0 0 0x10000 0>;
54 interrupts = <25 2 0 0>;
57 /* controller at 0x200000 */
63 bus-range = <0x0 0xff>;
64 interrupts = <20 2 0 0>;
66 pcie@0 {
71 reg = <0 0 0 0 0>;
72 interrupts = <20 2 0 0>;
[all …]
Dt2081si-post.dtsi37 alloc-ranges = <0 0 0x10000 0>;
42 alloc-ranges = <0 0 0x10000 0>;
47 alloc-ranges = <0 0 0x10000 0>;
54 interrupts = <25 2 0 0>;
57 /* controller at 0x240000 */
59 compatible = "fsl,t2080-pcie", "fsl,qoriq-pcie-v3.0", "fsl,qoriq-pcie";
63 bus-range = <0x0 0xff>;
64 interrupts = <20 2 0 0>;
66 pcie@0 {
67 reg = <0 0 0 0 0>;
[all …]
/kernel/linux/linux-6.6/arch/powerpc/boot/dts/fsl/
Db4si-post.dtsi37 alloc-ranges = <0 0 0x10000 0>;
42 alloc-ranges = <0 0 0x10000 0>;
47 alloc-ranges = <0 0 0x10000 0>;
54 interrupts = <25 2 0 0>;
57 /* controller at 0x200000 */
63 bus-range = <0x0 0xff>;
64 interrupts = <20 2 0 0>;
66 pcie@0 {
71 reg = <0 0 0 0 0>;
72 interrupts = <20 2 0 0>;
[all …]
Dt2081si-post.dtsi37 alloc-ranges = <0 0 0x10000 0>;
42 alloc-ranges = <0 0 0x10000 0>;
47 alloc-ranges = <0 0 0x10000 0>;
54 interrupts = <25 2 0 0>;
57 /* controller at 0x240000 */
59 compatible = "fsl,t2080-pcie", "fsl,qoriq-pcie-v3.0", "fsl,qoriq-pcie";
63 bus-range = <0x0 0xff>;
64 interrupts = <20 2 0 0>;
66 pcie@0 {
67 reg = <0 0 0 0 0>;
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/disp/dpu1/catalog/
Ddpu_7_2_sc7280.h12 .max_mixer_blendstages = 0x7,
22 .base = 0x0, .len = 0x2014,
24 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
25 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
26 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
27 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
28 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
35 .base = 0x15000, .len = 0x1e8,
40 .base = 0x16000, .len = 0x1e8,
45 .base = 0x17000, .len = 0x1e8,
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-s3c/
Dmach-qt2410.c50 { 0xe0000000, __phys_to_pfn(S3C2410_CS3+0x01000000), SZ_1M, MT_DEVICE }
58 [0] = {
59 .hwport = 0,
60 .flags = 0,
67 .flags = 0,
74 .flags = 0,
157 .default_display = 0,
159 .lpcsel = ((0xCE6) & ~7) | 1<<4,
165 [0] = DEFINE_RES_MEM(0x19000000, 17),
178 .dev_id = "s3c24xx_led.0",
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dbcm-hr2.dtsi45 #size-cells = <0>;
47 cpu0: cpu@0 {
51 reg = <0x0>;
64 ranges = <0x00000000 0x19000000 0x00023000>;
68 a9pll: arm_clk@0 {
69 #clock-cells = <0>;
72 reg = <0x0 0x1000>;
77 reg = <0x20200 0x100>;
84 reg = <0x20600 0x20>;
92 reg = <0x20620 0x20>;
[all …]
Darmada-xp-mv78260.dtsi27 #size-cells = <0>;
30 cpu@0 {
33 reg = <0>;
34 clocks = <&cpuclk 0>;
49 * MV78260 has 3 PCIe units Gen2.0: Two units can be
62 bus-range = <0x00 0xff>;
65 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
66 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
67 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
68 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/broadcom/
Dbcm-hr2.dtsi45 #size-cells = <0>;
47 cpu0: cpu@0 {
51 reg = <0x0>;
64 ranges = <0x00000000 0x19000000 0x00023000>;
68 a9pll: arm_clk@0 {
69 #clock-cells = <0>;
72 reg = <0x0 0x1000>;
77 reg = <0x20200 0x100>;
84 reg = <0x20600 0x20>;
92 reg = <0x20620 0x20>;
[all …]
/kernel/linux/linux-5.10/arch/mips/include/asm/sn/sn0/
Dkldir.h28 * 0x2000000 (32M) +-----------------------------------------+
30 * 0x1F80000 (31.5M) +-----------------------------------------+
32 * 0x1C00000 (30M) +-----------------------------------------+
34 * 0x0800000 (28M) +-----------------------------------------+
36 * 0x1B00000 (27M) +-----------------------------------------+
38 * 0x1A00000 (26M) +-----------------------------------------+
40 * 0x1800000 (24M) +-----------------------------------------+
42 * 0x1600000 (22M) +-----------------------------------------+
48 * 0x190000 (2M--) +-----------------------------------------+
51 * 0x34000 (208K) +-----------------------------------------+
[all …]
/kernel/linux/linux-6.6/arch/mips/include/asm/sn/sn0/
Dkldir.h28 * 0x2000000 (32M) +-----------------------------------------+
30 * 0x1F80000 (31.5M) +-----------------------------------------+
32 * 0x1C00000 (30M) +-----------------------------------------+
34 * 0x0800000 (28M) +-----------------------------------------+
36 * 0x1B00000 (27M) +-----------------------------------------+
38 * 0x1A00000 (26M) +-----------------------------------------+
40 * 0x1800000 (24M) +-----------------------------------------+
42 * 0x1600000 (22M) +-----------------------------------------+
48 * 0x190000 (2M--) +-----------------------------------------+
51 * 0x34000 (208K) +-----------------------------------------+
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/ath/ath10k/
Dcoredump.c18 {0x800, 0x810},
19 {0x820, 0x82C},
20 {0x830, 0x8F4},
21 {0x90C, 0x91C},
22 {0xA14, 0xA18},
23 {0xA84, 0xA94},
24 {0xAA8, 0xAD4},
25 {0xADC, 0xB40},
26 {0x1000, 0x10A4},
27 {0x10BC, 0x111C},
[all …]
/kernel/linux/linux-6.6/drivers/net/wireless/ath/ath10k/
Dcoredump.c18 {0x800, 0x810},
19 {0x820, 0x82C},
20 {0x830, 0x8F4},
21 {0x90C, 0x91C},
22 {0xA14, 0xA18},
23 {0xA84, 0xA94},
24 {0xAA8, 0xAD4},
25 {0xADC, 0xB40},
26 {0x1000, 0x10A4},
27 {0x10BC, 0x111C},
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/apple/
Dt600x-die0.dtsi3 * Devices used on die 0 on the Apple T6002 "M1 Ultra" SoC and present on
12 reg = <0x2 0x8e03c000 0x0 0x14000>;
21 reg = <0x2 0x8e100000 0x0 0xc000>,
22 <0x2 0x8e10c000 0x0 0x4>;
29 reg = <0x2 0x90820000 0x0 0x4000>;
33 gpio-ranges = <&pinctrl_smc 0 0 30>;
39 interrupts = <AIC_IRQ 0 743 IRQ_TYPE_LEVEL_HIGH>,
40 <AIC_IRQ 0 744 IRQ_TYPE_LEVEL_HIGH>,
41 <AIC_IRQ 0 745 IRQ_TYPE_LEVEL_HIGH>,
42 <AIC_IRQ 0 746 IRQ_TYPE_LEVEL_HIGH>,
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/mediatek/mt76/mt7915/
Dregs.h8 #define MT_MCU_WFDMA1_BASE 0x3000
11 #define MT_MCU_INT_EVENT MT_MCU_WFDMA1(0x108)
12 #define MT_MCU_INT_EVENT_DMA_STOPPED BIT(0)
17 #define MT_PLE_BASE 0x8000
20 #define MT_PLE_FL_Q0_CTRL MT_PLE(0x1b0)
21 #define MT_PLE_FL_Q1_CTRL MT_PLE(0x1b4)
22 #define MT_PLE_FL_Q2_CTRL MT_PLE(0x1b8)
23 #define MT_PLE_FL_Q3_CTRL MT_PLE(0x1bc)
25 #define MT_PLE_AC_QEMPTY(ac, n) MT_PLE(0x300 + 0x10 * (ac) + \
27 #define MT_PLE_AMSDU_PACK_MSDU_CNT(n) MT_PLE(0x10e0 + ((n) << 2))
[all …]

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