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/kernel/linux/linux-5.10/arch/arm/mach-omap2/
Dfb.c32 DEFINE_RES_MEM_NAMED(0x68008000u, 0x40, "vrfb-regs"),
33 DEFINE_RES_MEM_NAMED(0x70000000u, 0x4000000, "vrfb-area-0"),
34 DEFINE_RES_MEM_NAMED(0x74000000u, 0x4000000, "vrfb-area-1"),
35 DEFINE_RES_MEM_NAMED(0x78000000u, 0x4000000, "vrfb-area-2"),
36 DEFINE_RES_MEM_NAMED(0x7c000000u, 0x4000000, "vrfb-area-3"),
40 DEFINE_RES_MEM_NAMED(0x6C000180u, 0xc0, "vrfb-regs"),
41 DEFINE_RES_MEM_NAMED(0x70000000u, 0x4000000, "vrfb-area-0"),
42 DEFINE_RES_MEM_NAMED(0x74000000u, 0x4000000, "vrfb-area-1"),
43 DEFINE_RES_MEM_NAMED(0x78000000u, 0x4000000, "vrfb-area-2"),
44 DEFINE_RES_MEM_NAMED(0x7c000000u, 0x4000000, "vrfb-area-3"),
[all …]
/kernel/linux/linux-6.6/arch/arm/mach-omap2/
Dfb.c32 DEFINE_RES_MEM_NAMED(0x68008000u, 0x40, "vrfb-regs"),
33 DEFINE_RES_MEM_NAMED(0x70000000u, 0x4000000, "vrfb-area-0"),
34 DEFINE_RES_MEM_NAMED(0x74000000u, 0x4000000, "vrfb-area-1"),
35 DEFINE_RES_MEM_NAMED(0x78000000u, 0x4000000, "vrfb-area-2"),
36 DEFINE_RES_MEM_NAMED(0x7c000000u, 0x4000000, "vrfb-area-3"),
40 DEFINE_RES_MEM_NAMED(0x6C000180u, 0xc0, "vrfb-regs"),
41 DEFINE_RES_MEM_NAMED(0x70000000u, 0x4000000, "vrfb-area-0"),
42 DEFINE_RES_MEM_NAMED(0x74000000u, 0x4000000, "vrfb-area-1"),
43 DEFINE_RES_MEM_NAMED(0x78000000u, 0x4000000, "vrfb-area-2"),
44 DEFINE_RES_MEM_NAMED(0x7c000000u, 0x4000000, "vrfb-area-3"),
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/mtd/
Dti,am654-hbmc.txt23 reg = <0x0 0x47000000 0x0 0x100>;
31 mux-reg-masks = <0x4 0x2>; /* 0: reg 0x4, bit 1 */
37 reg = <0x0 0x47034000 0x0 0x100>,
38 <0x5 0x00000000 0x1 0x0000000>;
42 ranges = <0x0 0x0 0x5 0x00000000 0x4000000>, /* CS0 - 64MB */
43 <0x1 0x0 0x5 0x04000000 0x4000000>; /* CS1 - 64MB */
44 mux-controls = <&hbmc_mux 0>;
47 flash@0,0 {
49 reg = <0x0 0x0 0x4000000>;
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/mtd/
Dti,am654-hbmc.yaml31 "^flash@[0-1],[0-9a-f]+$":
54 reg = <0x0 0x47034000 0x0 0x100>,
55 <0x5 0x00000000 0x1 0x0000000>;
56 ranges = <0x0 0x0 0x5 0x00000000 0x4000000>, /* CS0 - 64MB */
57 <0x1 0x0 0x5 0x04000000 0x4000000>; /* CS1 - 64MB */
58 clocks = <&k3_clks 102 0>;
62 mux-controls = <&hbmc_mux 0>;
64 flash@0,0 {
66 reg = <0x0 0x0 0x4000000>;
Dmxicy,nand-ecc-engine.yaml36 reg = <0x43c30000 0x10000>, <0xa0000000 0x4000000>;
38 clocks = <&clkwizard 0>, <&clkwizard 1>, <&clkc 15>;
41 #size-cells = <0>;
43 flash@0 {
45 reg = <0>;
52 reg = <0x43c40000 0x10000>;
59 reg = <0x43c30000 0x10000>, <0xa0000000 0x4000000>;
61 clocks = <&clkwizard 0>, <&clkwizard 1>, <&clkc 15>;
64 #size-cells = <0>;
67 flash@0 {
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_7_2_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8
36 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
[all …]
Dgfx_8_0_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
Dgfx_8_1_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_7_2_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8
36 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
[all …]
Dgfx_8_0_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
Dgfx_8_1_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/compressed/
Dmisc.c16 * which should point to addresses in RAM and cleared to 0 on start.
40 int status, i = 0x4000000; in icedcc_putc()
43 if (--i < 0) in icedcc_putc()
46 asm volatile ("mrc p14, 0, %0, c0, c1, 0" : "=r" (status)); in icedcc_putc()
49 asm("mcr p14, 0, %0, c0, c5, 0" : : "r" (ch)); in icedcc_putc()
57 int status, i = 0x4000000; in icedcc_putc()
60 if (--i < 0) in icedcc_putc()
63 asm volatile ("mrc p14, 0, %0, c14, c0, 0" : "=r" (status)); in icedcc_putc()
66 asm("mcr p14, 0, %0, c8, c0, 0" : : "r" (ch)); in icedcc_putc()
73 int status, i = 0x4000000; in icedcc_putc()
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/compressed/
Dmisc.c16 * which should point to addresses in RAM and cleared to 0 on start.
36 int status, i = 0x4000000; in icedcc_putc()
39 if (--i < 0) in icedcc_putc()
42 asm volatile ("mrc p14, 0, %0, c0, c1, 0" : "=r" (status)); in icedcc_putc()
45 asm("mcr p14, 0, %0, c0, c5, 0" : : "r" (ch)); in icedcc_putc()
53 int status, i = 0x4000000; in icedcc_putc()
56 if (--i < 0) in icedcc_putc()
59 asm volatile ("mrc p14, 0, %0, c14, c0, 0" : "=r" (status)); in icedcc_putc()
62 asm("mcr p14, 0, %0, c8, c0, 0" : : "r" (ch)); in icedcc_putc()
69 int status, i = 0x4000000; in icedcc_putc()
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/spi/
Dti_qspi.txt23 parameters for Mode-0 and Mode-3 operations, which needs to be set up by
24 the bootloader (U-Boot). Default configuration only supports Mode-0
34 reg = <0x47900000 0x100>, <0x30000000 0x4000000>;
37 #size-cells = <0>;
45 reg = <0x4b300000 0x100>,
46 <0x5c000000 0x4000000>,
48 syscon-chipselects = <&scm_conf 0x558>;
50 #size-cells = <0>;
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/spi/
Dti_qspi.txt23 parameters for Mode-0 and Mode-3 operations, which needs to be set up by
24 the bootloader (U-Boot). Default configuration only supports Mode-0
34 reg = <0x47900000 0x100>, <0x30000000 0x4000000>;
37 #size-cells = <0>;
45 reg = <0x4b300000 0x100>,
46 <0x5c000000 0x4000000>,
48 syscon-chipselects = <&scm_conf 0x558>;
50 #size-cells = <0>;
/kernel/linux/linux-5.10/arch/mips/boot/dts/ingenic/
Djz4740.dtsi12 #size-cells = <0>;
14 cpu0: cpu@0 {
16 compatible = "ingenic,xburst-mxu1.0";
17 reg = <0>;
25 #address-cells = <0>;
33 reg = <0x10001000 0x14>;
44 #clock-cells = <0>;
49 #clock-cells = <0>;
55 reg = <0x10000000 0x100>;
65 reg = <0x10002000 0x1000>;
[all …]
Djz4725b.dtsi12 #size-cells = <0>;
14 cpu0: cpu@0 {
16 compatible = "ingenic,xburst-mxu1.0";
17 reg = <0>;
25 #address-cells = <0>;
33 reg = <0x10001000 0x14>;
44 #clock-cells = <0>;
49 #clock-cells = <0>;
55 reg = <0x10000000 0x100>;
65 reg = <0x10002000 0x1000>;
[all …]
/kernel/linux/linux-6.6/arch/mips/boot/dts/ingenic/
Djz4740.dtsi12 #size-cells = <0>;
14 cpu0: cpu@0 {
16 compatible = "ingenic,xburst-mxu1.0";
17 reg = <0>;
25 #address-cells = <0>;
33 reg = <0x10001000 0x14>;
44 #clock-cells = <0>;
49 #clock-cells = <0>;
55 reg = <0x10000000 0x100>;
65 reg = <0x10002000 0x1000>;
[all …]
Djz4725b.dtsi12 #size-cells = <0>;
14 cpu0: cpu@0 {
16 compatible = "ingenic,xburst-mxu1.0";
17 reg = <0>;
25 #address-cells = <0>;
33 reg = <0x10001000 0x14>;
44 #clock-cells = <0>;
49 #clock-cells = <0>;
55 reg = <0x10000000 0x100>;
65 reg = <0x10002000 0x1000>;
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/ti/
Dk3-j7200-som-p0.dtsi14 reg = <0x00 0x80000000 0x00 0x80000000>,
15 <0x08 0x80000000 0x00 0x80000000>;
24 reg = <0x00 0x9e800000 0x00 0x01800000>;
25 alignment = <0x1000>;
34 J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (B6) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */
35 J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C8) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */
36 J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (D6) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */
37 J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (D7) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */
38 J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (B7) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */
39 J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D8) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/microchip/
Dat91-lmu5000.dts20 reg = <0x20000000 0x4000000>;
28 main_clock: clock@0 {
43 pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>;
48 reg = <0x3 0x0 0x800000>;
62 kernel@0 {
64 reg = <0x0 0x400000>;
69 reg = <0x400000 0x3C00000>;
74 reg = <0x4000000 0x2000000>;
79 reg = <0x6000000 0x2000000>;
107 pinctrl-0 = <&pinctrl_ssc0_tx>;
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/reserved-memory/
Dshared-dma-pool.yaml82 size = <0x4000000>;
83 alignment = <0x2000>;
88 reg = <0x78000000 0x800000>;
93 reg = <0x50000000 0x4000000>;
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/smu/
Dsmu_7_1_1_sh_mask.h27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/smu/
Dsmu_7_1_1_sh_mask.h27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
[all …]
/kernel/linux/linux-6.6/arch/riscv/boot/dts/microchip/
Dmpfs-sev-kit.dts42 reg = <0x0 0x80000000 0x0 0x2000000>;
47 reg = <0x0 0xc4000000 0x0 0x4000000>;
52 reg = <0x0 0xd4000000 0x0 0x4000000>;
58 reg = <0x10 0x0 0x0 0x76000000>;

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