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/kernel/linux/linux-6.6/arch/arm64/boot/dts/ti/
Dk3-am65.dtsi54 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
55 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
56 <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
57 <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
58 <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
59 <0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* MSMC SRAM */
60 <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
62 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
63 <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,
64 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
[all …]
Dk3-j721s2.dtsi29 #size-cells = <0>;
42 cpu0: cpu@0 {
44 reg = <0x000>;
47 i-cache-size = <0xc000>;
50 d-cache-size = <0x8000>;
58 reg = <0x001>;
61 i-cache-size = <0xc000>;
64 d-cache-size = <0x8000>;
75 cache-size = <0x100000>;
118 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
[all …]
Dk3-j7200.dtsi25 #size-cells = <0>;
39 cpu0: cpu@0 {
41 reg = <0x000>;
44 i-cache-size = <0xc000>;
47 d-cache-size = <0x8000>;
55 reg = <0x001>;
58 i-cache-size = <0xc000>;
61 d-cache-size = <0x8000>;
72 cache-size = <0x100000>;
113 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
[all …]
Dk3-j721e.dtsi25 #size-cells = <0>;
39 cpu0: cpu@0 {
41 reg = <0x000>;
44 i-cache-size = <0xC000>;
47 d-cache-size = <0x8000>;
55 reg = <0x001>;
58 i-cache-size = <0xC000>;
61 d-cache-size = <0x8000>;
72 cache-size = <0x100000>;
114 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
[all …]
Dk3-j784s4.dtsi26 #size-cells = <0>;
65 cpu0: cpu@0 {
67 reg = <0x000>;
70 i-cache-size = <0xc000>;
73 d-cache-size = <0x8000>;
81 reg = <0x001>;
84 i-cache-size = <0xc000>;
87 d-cache-size = <0x8000>;
95 reg = <0x002>;
98 i-cache-size = <0xc000>;
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/ti/
Dk3-am65.dtsi68 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
69 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
70 <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
71 <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
72 <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
73 <0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* MSMC SRAM */
74 <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
76 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
77 <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,
78 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
[all …]
Dk3-j7200.dtsi39 #size-cells = <0>;
53 cpu0: cpu@0 {
55 reg = <0x000>;
58 i-cache-size = <0xc000>;
61 d-cache-size = <0x8000>;
69 reg = <0x001>;
72 i-cache-size = <0xc000>;
75 d-cache-size = <0x8000>;
85 cache-size = <0x100000>;
125 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
[all …]
Dk3-j721e.dtsi40 #size-cells = <0>;
54 cpu0: cpu@0 {
56 reg = <0x000>;
59 i-cache-size = <0xC000>;
62 d-cache-size = <0x8000>;
70 reg = <0x001>;
73 i-cache-size = <0xC000>;
76 d-cache-size = <0x8000>;
86 cache-size = <0x100000>;
127 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
[all …]
/kernel/linux/linux-6.6/arch/arm/mach-omap2/
Dsram.h57 #define OMAP2_SRAM_PA 0x40200000
58 #define OMAP3_SRAM_PA 0x40200000
/kernel/linux/linux-5.10/arch/arm/mach-omap2/
Dsram.h58 #define OMAP2_SRAM_PA 0x40200000
59 #define OMAP3_SRAM_PA 0x40200000
/kernel/linux/linux-5.10/arch/arm/mach-pxa/include/mach/
Dregs-uart.h11 #define FFRBR __REG(0x40100000) /* Receive Buffer Register (read only) */
12 #define FFTHR __REG(0x40100000) /* Transmit Holding Register (write only) */
13 #define FFIER __REG(0x40100004) /* Interrupt Enable Register (read/write) */
14 #define FFIIR __REG(0x40100008) /* Interrupt ID Register (read only) */
15 #define FFFCR __REG(0x40100008) /* FIFO Control Register (write only) */
16 #define FFLCR __REG(0x4010000C) /* Line Control Register (read/write) */
17 #define FFMCR __REG(0x40100010) /* Modem Control Register (read/write) */
18 #define FFLSR __REG(0x40100014) /* Line Status Register (read only) */
19 #define FFMSR __REG(0x40100018) /* Modem Status Register (read only) */
20 #define FFSPR __REG(0x4010001C) /* Scratch Pad Register (read/write) */
[all …]
Duncompress.h12 #define FFUART_BASE (0x40100000)
13 #define BTUART_BASE (0x40200000)
14 #define STUART_BASE (0x40700000)
67 uart_base = 0x10000000; /* nCS4 */ in arch_decomp_setup()
69 uart_is_pxa = 0; in arch_decomp_setup()
/kernel/linux/linux-6.6/arch/arm64/boot/dts/arm/
Dcorstone1000-mps3.dts18 reg = <0x40100000 0x10000>;
27 reg = <0x40200000 0x100000>;
/kernel/linux/linux-6.6/arch/powerpc/platforms/cell/spufs/
Dspu_restore_dump.h_shipped7 0x40800000,
8 0x409ff801,
9 0x24000080,
10 0x24fd8081,
11 0x1cd80081,
12 0x33001180,
13 0x42034003,
14 0x33800284,
15 0x1c010204,
16 0x40200000,
[all …]
Dspu_save_crt0.S18 .space SIZEOF_SPU_SPILL_REGS, 0x0
24 stqa $0, regs_spill + 0
47 .balignl 16, 0x40200000
49 stqd $16, 0($3)
53 andi $5, $4, 0x7F
62 il $0, 0
64 stqd $0, 0($SP)
74 brsl $0, main
78 * stop-and-signal with code=0.
84 stop 0x0
[all …]
Dspu_restore_crt0.S19 .space SIZEOF_SPU_SPILL_REGS, 0x0
28 il $0, 0
30 stqd $0, 0($SP)
40 brsl $0, main
52 .balignl 16, 0x40200000
54 lqd $16, 0($3)
58 andi $5, $4, 0x7F
64 lqa $0, regs_spill + 0
87 * following the 'stop 0x3ffc' have been modified at run
97 stop 0
[all …]
/kernel/linux/linux-5.10/arch/powerpc/platforms/cell/spufs/
Dspu_restore_dump.h_shipped7 0x40800000,
8 0x409ff801,
9 0x24000080,
10 0x24fd8081,
11 0x1cd80081,
12 0x33001180,
13 0x42034003,
14 0x33800284,
15 0x1c010204,
16 0x40200000,
[all …]
Dspu_save_crt0.S18 .space SIZEOF_SPU_SPILL_REGS, 0x0
24 stqa $0, regs_spill + 0
47 .balignl 16, 0x40200000
49 stqd $16, 0($3)
53 andi $5, $4, 0x7F
62 il $0, 0
64 stqd $0, 0($SP)
74 brsl $0, main
78 * stop-and-signal with code=0.
84 stop 0x0
[all …]
Dspu_restore_crt0.S19 .space SIZEOF_SPU_SPILL_REGS, 0x0
28 il $0, 0
30 stqd $0, 0($SP)
40 brsl $0, main
52 .balignl 16, 0x40200000
54 lqd $16, 0($3)
58 andi $5, $4, 0x7F
64 lqa $0, regs_spill + 0
87 * following the 'stop 0x3ffc' have been modified at run
97 stop 0
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/usb/
Dnxp,isp1760.yaml61 reg = <0x40200000 0x100000>;
/kernel/linux/linux-6.6/arch/arm64/boot/dts/qcom/
Dsa8540p.dtsi184 linux,pci-domain = <0>;
201 reg = <0x0 0x01c10000 0x0 0x3000>,
202 <0x0 0x40000000 0x0 0xf1d>,
203 <0x0 0x40000f20 0x0 0xa8>,
204 <0x0 0x40001000 0x0 0x1000>,
205 <0x0 0x40100000 0x0 0x100000>;
208 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
209 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1d00000>;
216 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 541 IRQ_TYPE_LEVEL_HIGH>,
217 <0 0 0 2 &intc 0 0 GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>,
[all …]
Dsa8540p-ride.dts34 regulators-0 {
163 pinctrl-0 = <&ethernet0_default>;
170 #size-cells = <0>;
174 compatible = "ethernet-phy-id0141.0dd4";
175 reg = <0x8>;
189 /* Set MODE[2:0] to RGMII_SGMII */
190 <0x12 0x14 0xfff8 0x4>,
191 /* Soft reset required after changing MODE[2:0] */
192 <0x12 0x14 0x7fff 0x8000>;
202 snps,map-to-dma-channel = <0x0>;
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/intel/pxa/
Dpxa2xx.dtsi64 reg = <0x40d00000 0xd0>;
69 #address-cells = <0x1>;
70 #size-cells = <0x1>;
71 reg = <0x40e00000 0x10000>;
73 #gpio-cells = <0x2>;
77 #interrupt-cells = <0x2>;
81 reg = <0x40e00000 0x4>;
85 reg = <0x40e00004 0x4>;
89 reg = <0x40e00008 0x4>;
92 reg = <0x40e0000c 0x4>;
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dpxa2xx.dtsi64 reg = <0x40d00000 0xd0>;
69 #address-cells = <0x1>;
70 #size-cells = <0x1>;
71 reg = <0x40e00000 0x10000>;
73 #gpio-cells = <0x2>;
77 #interrupt-cells = <0x2>;
81 reg = <0x40e00000 0x4>;
85 reg = <0x40e00004 0x4>;
89 reg = <0x40e00008 0x4>;
92 reg = <0x40e0000c 0x4>;
[all …]
Dmps2.dtsi53 #clock-cells = <0>;
59 #clock-cells = <0>;
65 #clock-cells = <0>;
71 #clock-cells = <0>;
77 #clock-cells = <0>;
84 #clock-cells = <0>;
92 #clock-cells = <0>;
100 #clock-cells = <0>;
108 #clock-cells = <0>;
116 #clock-cells = <0>;
[all …]

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