Searched +full:0 +full:x43100000 (Results 1 – 9 of 9) sorted by relevance
8 #define PXA_CS0_PHYS 0x000000009 #define PXA_CS1_PHYS 0x0400000010 #define PXA_CS2_PHYS 0x0800000011 #define PXA_CS3_PHYS 0x0C00000012 #define PXA_CS4_PHYS 0x1000000013 #define PXA_CS5_PHYS 0x1400000015 #define PXA300_CS0_PHYS 0x00000000 /* PXA300/PXA310 _only_ */16 #define PXA300_CS1_PHYS 0x30000000 /* PXA300/PXA310 _only_ */17 #define PXA3xx_CS2_PHYS 0x1000000018 #define PXA3xx_CS3_PHYS 0x14000000[all …]
66 minimum: 071 - minimum: 0156 reg = <0xd0000 0x54>;158 #size-cells = <0>;160 clocks = <&coredivclk 0>;162 nand@0 {163 reg = <0>;165 nand-rb = <0>;177 partition@0 {179 reg = <0x00000000 0x40000000>;[all …]
15 - #size-cells: shall be set to 0.38 - reg: shall contain the native Chip Select ids (0-3).39 - nand-rb: see nand-controller.yaml (0-1).68 reg = <0xd0000 0x54>;70 #size-cells = <0>;72 clocks = <&coredivclk 0>;74 nand@0 {75 reg = <0>;77 nand-rb = <0>;89 partition@0 {[all …]
6 ((gpio <= 2) ? (0x00b4 + 4 * gpio) : \7 (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \8 (gpio <= 98) ? (0x0400 + 4 * (gpio - 27)) : \9 (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \10 0)12 ((gpio <= 1) ? (0x674 + 4 * gpio) : \13 (gpio <= 6) ? (0x2dc + 4 * gpio) : \14 0)17 ((gpio <= 2) ? (0x00b4 + 4 * gpio) : \18 (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \[all …]
54 [0] = {55 .start = 0x41100000,56 .end = 0x41100fff,66 static u64 pxamci_dmamask = 0xffffffffUL;70 .id = 0,73 .coherent_dma_mask = 0xffffffff,95 [0] = {96 .start = 0x40600000,97 .end = 0x4060ffff,107 static u64 udc_dma_mask = ~(u32)0;[all …]
37 #define FLOAT_ZERO 0x0000000038 #define FLOAT_ONE 0x3f80000039 #define FLOAT_TWO 0x4000000040 #define FLOAT_THREE 0x4040000041 #define FLOAT_FIVE 0x40a0000042 #define FLOAT_SIX 0x40c0000043 #define FLOAT_EIGHT 0x4100000044 #define FLOAT_MINUS_5 0xc0a0000046 #define UNSOL_TAG_DSP 0x1655 #define MASTERCONTROL 0x80[all …]