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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dnvidia,tegra210-car.txt27 reg = <0x60006000 0x1000>;
43 #size-cells = <0>;
48 #clock-cells = <0>;
Dnvidia,tegra30-car.txt27 reg = <0x60006000 0x1000>;
43 #size-cells = <0>;
45 osc: clock@0 {
47 reg = <0>;
48 #clock-cells = <0>;
55 #clock-cells = <0>;
Dnvidia,tegra114-car.txt27 reg = <0x60006000 0x1000>;
43 #size-cells = <0>;
45 osc: clock@0 {
47 reg = <0>;
48 #clock-cells = <0>;
55 #clock-cells = <0>;
Dnvidia,tegra20-car.txt27 reg = <0x60006000 0x1000>;
43 #size-cells = <0>;
45 osc: clock@0 {
47 reg = <0>;
48 #clock-cells = <0>;
55 #clock-cells = <0>;
Dnvidia,tegra124-car.txt51 reg = <0x60006000 0x1000>;
68 #size-cells = <0>;
70 osc: clock@0 {
72 reg = <0>;
73 #clock-cells = <0>;
80 #clock-cells = <0>;
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/
Dnvidia,tegra20-car.yaml89 reg = <0x60006000 0x1000>;
Dnvidia,tegra124-car.yaml49 "^emc-timings-[0-9]+$":
59 "^timing-[0-9]+$":
107 reg = <0x60006000 0x1000>;
/kernel/linux/linux-5.10/arch/arm/mach-tegra/
Diomap.h16 #define TEGRA_IRAM_BASE 0x40000000
19 #define TEGRA_ARM_PERIF_BASE 0x50040000
22 #define TEGRA_ARM_INT_DIST_BASE 0x50041000
25 #define TEGRA_TMR1_BASE 0x60005000
28 #define TEGRA_TMR2_BASE 0x60005008
31 #define TEGRA_TMRUS_BASE 0x60005010
34 #define TEGRA_TMR3_BASE 0x60005050
37 #define TEGRA_TMR4_BASE 0x60005058
40 #define TEGRA_CLK_RESET_BASE 0x60006000
43 #define TEGRA_FLOW_CTRL_BASE 0x60007000
[all …]
/kernel/linux/linux-6.6/arch/arm/mach-tegra/
Diomap.h16 #define TEGRA_IRAM_BASE 0x40000000
19 #define TEGRA_ARM_PERIF_BASE 0x50040000
22 #define TEGRA_ARM_INT_DIST_BASE 0x50041000
25 #define TEGRA_TMR1_BASE 0x60005000
28 #define TEGRA_TMR2_BASE 0x60005008
31 #define TEGRA_TMRUS_BASE 0x60005010
34 #define TEGRA_TMR3_BASE 0x60005050
37 #define TEGRA_TMR4_BASE 0x60005058
40 #define TEGRA_CLK_RESET_BASE 0x60006000
43 #define TEGRA_FLOW_CTRL_BASE 0x60007000
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/
Dcortina,gemini-ethernet.txt23 - port0: contains the resources for ethernet port 0
59 reg = <0x60000000 0x4000>, /* Global registers, queue */
60 <0x60004000 0x2000>, /* V-bit */
61 <0x60006000 0x2000>; /* A-bit */
67 gmac0: ethernet-port@0 {
69 reg = <0x60008000 0x2000>, /* Port 0 DMA/TOE */
70 <0x6000a000 0x2000>; /* Port 0 GMAC */
82 reg = <0x6000c000 0x2000>, /* Port 1 DMA/TOE */
83 <0x6000e000 0x2000>; /* Port 1 GMAC */
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/
Dcortina,gemini-ethernet.yaml38 "^ethernet-port@[0-9]+$":
92 #size-cells = <0>;
106 reg = <0x60000000 0x4000>, /* Global registers, queue */
107 <0x60004000 0x2000>, /* V-bit */
108 <0x60006000 0x2000>; /* A-bit */
113 gmac0: ethernet-port@0 {
115 reg = <0x60008000 0x2000>, /* Port 0 DMA/TOE */
116 <0x6000a000 0x2000>; /* Port 0 GMAC */
128 reg = <0x6000c000 0x2000>, /* Port 1 DMA/TOE */
129 <0x6000e000 0x2000>; /* Port 1 GMAC */
/kernel/linux/linux-6.6/arch/arm/include/debug/
Dtegra.S21 #define TEGRA_CLK_RESET_BASE 0x60006000
22 #define TEGRA_APB_MISC_BASE 0x70000000
23 #define TEGRA_UARTA_BASE 0x70006000
24 #define TEGRA_UARTB_BASE 0x70006040
25 #define TEGRA_UARTC_BASE 0x70006200
26 #define TEGRA_UARTD_BASE 0x70006300
27 #define TEGRA_UARTE_BASE 0x70006400
28 #define TEGRA_PMC_BASE 0x7000e400
30 #define TEGRA_CLK_RST_DEVICES_L (TEGRA_CLK_RESET_BASE + 0x04)
31 #define TEGRA_CLK_RST_DEVICES_H (TEGRA_CLK_RESET_BASE + 0x08)
[all …]
/kernel/linux/linux-5.10/arch/arm/include/debug/
Dtegra.S21 #define TEGRA_CLK_RESET_BASE 0x60006000
22 #define TEGRA_APB_MISC_BASE 0x70000000
23 #define TEGRA_UARTA_BASE 0x70006000
24 #define TEGRA_UARTB_BASE 0x70006040
25 #define TEGRA_UARTC_BASE 0x70006200
26 #define TEGRA_UARTD_BASE 0x70006300
27 #define TEGRA_UARTE_BASE 0x70006400
28 #define TEGRA_PMC_BASE 0x7000e400
30 #define TEGRA_CLK_RST_DEVICES_L (TEGRA_CLK_RESET_BASE + 0x04)
31 #define TEGRA_CLK_RST_DEVICES_H (TEGRA_CLK_RESET_BASE + 0x08)
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/thermal/
Dnvidia,tegra124-soctherm.txt61 TEGRA_SOCTHERM_THROT_LEVEL_NONE (0%)
73 the property is missing. A value of 0 will interrupt on every OC alarm.
78 the counter is cleared and filter is rearmed. Default value is 0.
81 is 0.
106 reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */
107 0x0 0x60006000 0x0 0x400 /* CAR reg_base */
159 nvidia,throttle-period-us = <0>;
171 reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */
172 0x0 0x70040000 0x0 0x200>; /* CCROC reg_base */;
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/thermal/
Dnvidia,tegra124-soctherm.yaml88 minimum: 0
99 - 0
115 # none (0%, TEGRA_SOCTHERM_THROT_LEVEL_NONE)
116 - 0
130 property is missing. A value of 0 will interrupt on every OC
143 default: 0
148 default: 0
176 const: 0
240 reg = <0x700e2000 0x600>, /* SOC_THERM reg_base */
241 <0x60006000 0x400>; /* CAR reg_base */
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dgemini.dtsi23 pinctrl-0 = <&pflash_default_pins>;
33 reg = <0x40000000 0x1000>;
41 offset = <0x0c>;
43 mask = <0xC0000000>;
51 pinctrl-0 = <&dram_default_pins>, <&system_default_pins>,
161 reg = <0x41000000 0x1000>;
170 reg = <0x42000000 0x100>;
175 pinctrl-0 = <&uart_default_pins>;
181 reg = <0x43000000 0x1000>;
195 reg = <0x45000000 0x100>;
[all …]
Dtegra124.dtsi19 reg = <0x0 0x80000000 0x0 0x0>;
25 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
26 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
27 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */
34 interrupt-map-mask = <0 0 0 0>;
35 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
37 bus-range = <0x00 0xff>;
41 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */
42 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */
43 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
[all …]
Dtegra114.dtsi17 reg = <0x80000000 0x0>;
22 reg = <0x50000000 0x00028000>;
35 ranges = <0x54000000 0x54000000 0x01000000>;
39 reg = <0x54140000 0x00040000>;
50 reg = <0x54180000 0x00040000>;
60 reg = <0x54200000 0x00040000>;
70 nvidia,head = <0>;
79 reg = <0x54240000 0x00040000>;
98 reg = <0x54280000 0x00040000>;
110 reg = <0x54300000 0x00040000>;
[all …]
Dtegra20.dtsi15 memory@0 {
17 reg = <0 0>;
22 reg = <0x40000000 0x40000>;
25 ranges = <0 0x40000000 0x40000>;
28 reg = <0x400 0x3fc00>;
35 reg = <0x50000000 0x00024000>;
47 ranges = <0x54000000 0x54000000 0x04000000>;
51 reg = <0x54040000 0x00040000>;
60 reg = <0x54080000 0x00040000>;
69 reg = <0x540c0000 0x00040000>;
[all …]
Dtegra30.dtsi17 reg = <0x80000000 0x0>;
23 reg = <0x00003000 0x00000800>, /* PADS registers */
24 <0x00003800 0x00000200>, /* AFI registers */
25 <0x10000000 0x10000000>; /* configuration space */
32 interrupt-map-mask = <0 0 0 0>;
33 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
35 bus-range = <0x00 0xff>;
39 ranges = <0x02000000 0 0x00000000 0x00000000 0 0x00001000>, /* port 0 configuration space */
40 <0x02000000 0 0x00001000 0x00001000 0 0x00001000>, /* port 1 configuration space */
41 <0x02000000 0 0x00004000 0x00004000 0 0x00001000>, /* port 2 configuration space */
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/gemini/
Dgemini.dtsi23 pinctrl-0 = <&pflash_default_pins>;
31 reg = <0x40000000 0x1000>;
39 offset = <0x0c>;
41 mask = <0xC0000000>;
49 pinctrl-0 = <&dram_default_pins>, <&system_default_pins>,
159 reg = <0x41000000 0x1000>;
168 reg = <0x42000000 0x100>;
173 pinctrl-0 = <&uart_default_pins>;
179 reg = <0x43000000 0x1000>;
193 reg = <0x45000000 0x100>;
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/nvidia/
Dtegra124.dtsi21 reg = <0x0 0x80000000 0x0 0x0>;
27 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
28 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
29 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */
36 interrupt-map-mask = <0 0 0 0>;
37 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
39 bus-range = <0x00 0xff>;
43 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */
44 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */
45 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
[all …]
Dtegra114.dtsi17 reg = <0x80000000 0x0>;
22 reg = <0x40000000 0x40000>;
25 ranges = <0 0x40000000 0x40000>;
28 reg = <0x400 0x3fc00>;
35 reg = <0x50000000 0x00028000>;
48 ranges = <0x54000000 0x54000000 0x01000000>;
52 reg = <0x54140000 0x00040000>;
63 reg = <0x54180000 0x00040000>;
73 reg = <0x54200000 0x00040000>;
83 nvidia,head = <0>;
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/nvidia/
Dtegra210.dtsi21 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
22 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
23 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */
30 interrupt-map-mask = <0 0 0 0>;
31 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
33 bus-range = <0x00 0xff>;
37 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */
38 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */
39 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
40 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/nvidia/
Dtegra210.dtsi21 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
22 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
23 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */
30 interrupt-map-mask = <0 0 0 0>;
31 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
33 bus-range = <0x00 0xff>;
37 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */
38 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */
39 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
40 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */
[all …]

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