Home
last modified time | relevance | path

Searched +full:0 +full:x90000 (Results 1 – 25 of 149) sorted by relevance

123456

/kernel/linux/linux-6.6/drivers/net/wireless/mediatek/mt76/mt76x2/
Dmcu.h12 #define MT_MCU_CPU_CTL 0x0704
13 #define MT_MCU_CLOCK_CTL 0x0708
14 #define MT_MCU_PCIE_REMAP_BASE1 0x0740
15 #define MT_MCU_PCIE_REMAP_BASE2 0x0744
16 #define MT_MCU_PCIE_REMAP_BASE3 0x0748
18 #define MT_MCU_ROM_PATCH_OFFSET 0x80000
19 #define MT_MCU_ROM_PATCH_ADDR 0x90000
21 #define MT_MCU_ILM_OFFSET 0x80000
23 #define MT_MCU_DLM_OFFSET 0x100000
24 #define MT_MCU_DLM_ADDR 0x90000
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/mediatek/mt76/mt76x2/
Dmcu.h12 #define MT_MCU_CPU_CTL 0x0704
13 #define MT_MCU_CLOCK_CTL 0x0708
14 #define MT_MCU_PCIE_REMAP_BASE1 0x0740
15 #define MT_MCU_PCIE_REMAP_BASE2 0x0744
16 #define MT_MCU_PCIE_REMAP_BASE3 0x0748
18 #define MT_MCU_ROM_PATCH_OFFSET 0x80000
19 #define MT_MCU_ROM_PATCH_ADDR 0x90000
21 #define MT_MCU_ILM_OFFSET 0x80000
23 #define MT_MCU_DLM_OFFSET 0x100000
24 #define MT_MCU_DLM_ADDR 0x90000
[all …]
/kernel/linux/linux-5.10/Documentation/x86/
Dboot.rst28 Protocol 2.02 (Kernel 2.4.0-test3-pre3) New command line protocol.
99 0A0000 +------------------------+
121 0x100000 ("high memory"), and the kernel real-mode block (boot sector,
123 0x10000 and end of low memory. Unfortunately, in protocols 2.00 and
124 2.01 the 0x90000+ memory range is still used internally by the kernel;
139 0x90000 segment, the boot loader should make sure not to use memory
140 above the 0x9A000 point; too many BIOSes will break above that point.
149 0A0000 +------------------------+
180 following header at offset 0x01f1. The real-mode code can total up to
195 01FE/2 ALL boot_flag 0xAA55 magic number
[all …]
/kernel/linux/linux-6.6/Documentation/arch/x86/
Dboot.rst28 Protocol 2.02 (Kernel 2.4.0-test3-pre3) New command line protocol.
99 0A0000 +------------------------+
121 0x100000 ("high memory"), and the kernel real-mode block (boot sector,
123 0x10000 and end of low memory. Unfortunately, in protocols 2.00 and
124 2.01 the 0x90000+ memory range is still used internally by the kernel;
139 0x90000 segment, the boot loader should make sure not to use memory
140 above the 0x9A000 point; too many BIOSes will break above that point.
149 0A0000 +------------------------+
180 following header at offset 0x01f1. The real-mode code can total up to
195 01FE/2 ALL boot_flag 0xAA55 magic number
[all …]
/kernel/linux/linux-5.10/drivers/clk/imx/
Dclk-imx8qxp-lpcg.h11 #define LSIO_PWM_0_LPCG 0x00000
12 #define LSIO_PWM_1_LPCG 0x10000
13 #define LSIO_PWM_2_LPCG 0x20000
14 #define LSIO_PWM_3_LPCG 0x30000
15 #define LSIO_PWM_4_LPCG 0x40000
16 #define LSIO_PWM_5_LPCG 0x50000
17 #define LSIO_PWM_6_LPCG 0x60000
18 #define LSIO_PWM_7_LPCG 0x70000
19 #define LSIO_GPIO_0_LPCG 0x80000
20 #define LSIO_GPIO_1_LPCG 0x90000
[all …]
/kernel/linux/linux-6.6/drivers/clk/imx/
Dclk-imx8qxp-lpcg.h11 #define LSIO_PWM_0_LPCG 0x00000
12 #define LSIO_PWM_1_LPCG 0x10000
13 #define LSIO_PWM_2_LPCG 0x20000
14 #define LSIO_PWM_3_LPCG 0x30000
15 #define LSIO_PWM_4_LPCG 0x40000
16 #define LSIO_PWM_5_LPCG 0x50000
17 #define LSIO_PWM_6_LPCG 0x60000
18 #define LSIO_PWM_7_LPCG 0x70000
19 #define LSIO_GPIO_0_LPCG 0x80000
20 #define LSIO_GPIO_1_LPCG 0x90000
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dkirkwood-openblocks_a6.dts13 reg = <0x00000000 0x20000000>;
40 reg = <0x30>;
45 pinctrl-0 = <&pmx_dip_switches>;
95 pinctrl-0 = <&pmx_leds>;
116 pinctrl-0 = <&pmx_gpio_init>;
119 #size-cells = <0>;
133 partition@0 {
135 reg = <0x0 0x90000>;
140 reg = <0x90000 0x44000>;
145 reg = <0xd4000 0x20000>;
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/marvell/
Dkirkwood-openblocks_a6.dts13 reg = <0x00000000 0x20000000>;
40 reg = <0x30>;
45 pinctrl-0 = <&pmx_dip_switches>;
95 pinctrl-0 = <&pmx_leds>;
116 pinctrl-0 = <&pmx_gpio_init>;
119 #size-cells = <0>;
133 partition@0 {
135 reg = <0x0 0x90000>;
140 reg = <0x90000 0x44000>;
145 reg = <0xd4000 0x20000>;
[all …]
/kernel/linux/linux-6.6/arch/arm/mach-imx/
Dmx3x.h36 #define MX3x_L2CC_BASE_ADDR 0x30000000
42 #define MX3x_AIPS1_BASE_ADDR 0x43f00000
44 #define MX3x_MAX_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x04000)
45 #define MX3x_EVTMON_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x08000)
46 #define MX3x_CLKCTL_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x0c000)
47 #define MX3x_ETB_SLOT4_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x10000)
48 #define MX3x_ETB_SLOT5_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x14000)
49 #define MX3x_ECT_CTIO_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x18000)
50 #define MX3x_I2C_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x80000)
51 #define MX3x_I2C3_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x84000)
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-imx/
Dmx3x.h36 #define MX3x_L2CC_BASE_ADDR 0x30000000
42 #define MX3x_AIPS1_BASE_ADDR 0x43f00000
44 #define MX3x_MAX_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x04000)
45 #define MX3x_EVTMON_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x08000)
46 #define MX3x_CLKCTL_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x0c000)
47 #define MX3x_ETB_SLOT4_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x10000)
48 #define MX3x_ETB_SLOT5_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x14000)
49 #define MX3x_ECT_CTIO_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x18000)
50 #define MX3x_I2C_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x80000)
51 #define MX3x_I2C3_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x84000)
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/security/tpm/
Dtpm_tis_mmio.txt15 - reg: The location of the MMIO registers, should be at least 0x5000 bytes
22 reg = <0x90000 0x5000>;
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/security/tpm/
Dtpm_tis_mmio.txt15 - reg: The location of the MMIO registers, should be at least 0x5000 bytes
22 reg = <0x90000 0x5000>;
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/clock/
Dqcom,msm8996-apcc.yaml13 Qualcomm CPU clock controller for MSM8996 CPUs, clock 0 is for Power cluster
50 reg = <0x6400000 0x90000>;
Dqcom,gcc-msm8994.yaml48 reg = <0x00300000 0x90000>;
Dqcom,gcc-msm8996.yaml29 - description: PCIe 0 PIPE clock (optional)
33 - description: UFS RX symbol 0 clock (optional)
35 - description: UFS TX symbol 0 clock (optional)
66 reg = <0x300000 0x90000>;
Dqcom,gcc-msm8916.yaml33 - description: DSI phy instance 0 dsi clock
34 - description: DSI phy instance 0 byte clock
64 reg = <0x300000 0x90000>;
/kernel/linux/linux-5.10/arch/arm64/boot/dts/freescale/
Dqoriq-fman3-0-10g-0.dtsi3 * QorIQ FMan v3 10g port #0 device tree
11 cell-index = <0x10>;
13 reg = <0x90000 0x1000>;
18 cell-index = <0x30>;
20 reg = <0xb0000 0x1000>;
25 cell-index = <0x8>;
27 reg = <0xf0000 0x1000>;
34 #size-cells = <0>;
36 reg = <0xf1000 0x1000>;
38 pcsphy6: ethernet-phy@0 {
[all …]
Dqoriq-bman-portals.dtsi14 bman-portal@0 {
20 reg = <0x0 0x4000>, <0x4000000 0x4000>;
26 reg = <0x10000 0x4000>, <0x4010000 0x4000>;
32 reg = <0x20000 0x4000>, <0x4020000 0x4000>;
38 reg = <0x30000 0x4000>, <0x4030000 0x4000>;
44 reg = <0x40000 0x4000>, <0x4040000 0x4000>;
50 reg = <0x50000 0x4000>, <0x4050000 0x4000>;
56 reg = <0x60000 0x4000>, <0x4060000 0x4000>;
62 reg = <0x70000 0x4000>, <0x4070000 0x4000>;
68 reg = <0x80000 0x4000>, <0x4080000 0x4000>;
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/freescale/
Dqoriq-fman3-0-10g-0.dtsi3 * QorIQ FMan v3 10g port #0 device tree
11 cell-index = <0x10>;
13 reg = <0x90000 0x1000>;
18 cell-index = <0x30>;
20 reg = <0xb0000 0x1000>;
25 cell-index = <0x8>;
27 reg = <0xf0000 0x1000>;
34 #size-cells = <0>;
36 reg = <0xf1000 0x1000>;
38 pcsphy6: ethernet-phy@0 {
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dqcom,msm8996-apcc.yaml13 Qualcomm CPU clock controller for MSM8996 CPUs, clock 0 is for Power cluster
52 reg = <0x6400000 0x90000>;
Dqcom,gcc-msm8996.yaml30 - description: PCIe 0 PIPE clock (optional)
34 - description: UFS RX symbol 0 clock (optional)
36 - description: UFS TX symbol 0 clock (optional)
84 reg = <0x300000 0x90000>;
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/
Dqcom,ipq4019-mdio.yaml23 const: 0
40 #size-cells = <0>;
42 reg = <0x90000 0x64>;
44 ethphy0: ethernet-phy@0 {
45 reg = <0>;
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/crypto/
Dmarvell-cesa.txt37 reg = <0x90000 0x10000>;
43 marvell,crypto-sram-size = <0x600>;
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/crypto/
Dmarvell-cesa.txt37 reg = <0x90000 0x10000>;
43 marvell,crypto-sram-size = <0x600>;
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/net/
Dqcom,ipq4019-mdio.yaml29 const: 0
79 #size-cells = <0>;
81 reg = <0x90000 0x64>;
83 ethphy0: ethernet-phy@0 {
84 reg = <0>;

123456