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/kernel/linux/linux-5.10/arch/arm/mach-nspire/
Dmmio.h8 #define NSPIRE_MISC_PHYS_BASE 0x900A0000
9 #define NSPIRE_MISC_HWRESET 0x08
11 #define NSPIRE_PWR_PHYS_BASE 0x900B0000
12 #define NSPIRE_PWR_VIRT_BASE 0xFEEB0000
13 #define NSPIRE_PWR_BUS_DISABLE1 0x18
14 #define NSPIRE_PWR_BUS_DISABLE2 0x20
16 #define NSPIRE_LCD_PHYS_BASE 0xC0000000
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/mfd/
Dti,nspire-misc.yaml44 reg = <0x900a0000 0x1000>;
48 offset = <0x08>;
49 value = <0x02>;
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dnspire.dtsi14 cpu@0 {
19 bootrom: bootrom@0 {
20 reg = <0x00000000 0x80000>;
25 reg = <0xA4000000 0x20000>;
29 #clock-cells = <0>;
35 #clock-cells = <0>;
36 reg = <0x900B0024 0x4>;
40 #clock-cells = <0>;
41 reg = <0x900B0024 0x4>;
46 #clock-cells = <0>;
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/nspire/
Dnspire.dtsi13 #size-cells = <0>;
15 cpu@0 {
18 reg = <0>;
22 bootrom: bootrom@0 {
23 reg = <0x00000000 0x80000>;
28 reg = <0xa4000000 0x20000>; /* 128k */
31 ranges = <0 0xa4000000 0x20000>;
33 sram@0 {
34 reg = <0x0 0x20000>;
39 #clock-cells = <0>;
[all …]