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/kernel/linux/linux-6.6/drivers/net/wireless/ath/ath9k/
Dreg_aic.h20 #define AR_SM_BASE 0xa200
21 #define AR_SM1_BASE 0xb200
22 #define AR_AGC_BASE 0x9e00
24 #define AR_PHY_AIC_CTRL_0_B0 (AR_SM_BASE + 0x4b0)
25 #define AR_PHY_AIC_CTRL_1_B0 (AR_SM_BASE + 0x4b4)
26 #define AR_PHY_AIC_CTRL_2_B0 (AR_SM_BASE + 0x4b8)
27 #define AR_PHY_AIC_CTRL_3_B0 (AR_SM_BASE + 0x4bc)
28 #define AR_PHY_AIC_CTRL_4_B0 (AR_SM_BASE + 0x4c0)
30 #define AR_PHY_AIC_STAT_0_B0 (AR_SM_BASE + 0x4c4)
31 #define AR_PHY_AIC_STAT_1_B0 (AR_SM_BASE + 0x4c8)
[all …]
Dar9002_phy.h19 #define AR_PHY_TEST 0x9800
20 #define PHY_AGC_CLR 0x10000000
21 #define RFSILENT_BB 0x00002000
23 #define AR_PHY_TURBO 0x9804
24 #define AR_PHY_FC_TURBO_MODE 0x00000001
25 #define AR_PHY_FC_TURBO_SHORT 0x00000002
26 #define AR_PHY_FC_DYN2040_EN 0x00000004
27 #define AR_PHY_FC_DYN2040_PRI_ONLY 0x00000008
28 #define AR_PHY_FC_DYN2040_PRI_CH 0x00000010
30 #define AR_PHY_FC_DYN2040_EXT_CH 0x00000020
[all …]
Dar9003_phy.h23 #define AR_CHAN_BASE 0x9800
25 #define AR_PHY_TIMING1 (AR_CHAN_BASE + 0x0)
26 #define AR_PHY_TIMING2 (AR_CHAN_BASE + 0x4)
27 #define AR_PHY_TIMING3 (AR_CHAN_BASE + 0x8)
28 #define AR_PHY_TIMING4 (AR_CHAN_BASE + 0xc)
29 #define AR_PHY_TIMING5 (AR_CHAN_BASE + 0x10)
30 #define AR_PHY_TIMING6 (AR_CHAN_BASE + 0x14)
31 #define AR_PHY_TIMING11 (AR_CHAN_BASE + 0x18)
32 #define AR_PHY_SPUR_REG (AR_CHAN_BASE + 0x1c)
33 #define AR_PHY_RX_IQCAL_CORR_B0 (AR_CHAN_BASE + 0xdc)
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/ath/ath9k/
Dreg_aic.h20 #define AR_SM_BASE 0xa200
21 #define AR_SM1_BASE 0xb200
22 #define AR_AGC_BASE 0x9e00
24 #define AR_PHY_AIC_CTRL_0_B0 (AR_SM_BASE + 0x4b0)
25 #define AR_PHY_AIC_CTRL_1_B0 (AR_SM_BASE + 0x4b4)
26 #define AR_PHY_AIC_CTRL_2_B0 (AR_SM_BASE + 0x4b8)
27 #define AR_PHY_AIC_CTRL_3_B0 (AR_SM_BASE + 0x4bc)
28 #define AR_PHY_AIC_CTRL_4_B0 (AR_SM_BASE + 0x4c0)
30 #define AR_PHY_AIC_STAT_0_B0 (AR_SM_BASE + 0x4c4)
31 #define AR_PHY_AIC_STAT_1_B0 (AR_SM_BASE + 0x4c8)
[all …]
Dar9002_phy.h19 #define AR_PHY_TEST 0x9800
20 #define PHY_AGC_CLR 0x10000000
21 #define RFSILENT_BB 0x00002000
23 #define AR_PHY_TURBO 0x9804
24 #define AR_PHY_FC_TURBO_MODE 0x00000001
25 #define AR_PHY_FC_TURBO_SHORT 0x00000002
26 #define AR_PHY_FC_DYN2040_EN 0x00000004
27 #define AR_PHY_FC_DYN2040_PRI_ONLY 0x00000008
28 #define AR_PHY_FC_DYN2040_PRI_CH 0x00000010
30 #define AR_PHY_FC_DYN2040_EXT_CH 0x00000020
[all …]
Dar9003_phy.h23 #define AR_CHAN_BASE 0x9800
25 #define AR_PHY_TIMING1 (AR_CHAN_BASE + 0x0)
26 #define AR_PHY_TIMING2 (AR_CHAN_BASE + 0x4)
27 #define AR_PHY_TIMING3 (AR_CHAN_BASE + 0x8)
28 #define AR_PHY_TIMING4 (AR_CHAN_BASE + 0xc)
29 #define AR_PHY_TIMING5 (AR_CHAN_BASE + 0x10)
30 #define AR_PHY_TIMING6 (AR_CHAN_BASE + 0x14)
31 #define AR_PHY_TIMING11 (AR_CHAN_BASE + 0x18)
32 #define AR_PHY_SPUR_REG (AR_CHAN_BASE + 0x1c)
33 #define AR_PHY_RX_IQCAL_CORR_B0 (AR_CHAN_BASE + 0xdc)
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/
Dqcom,qmp-usb3-dp-phy.yaml81 "^usb3-phy@[0-9a-f]+$":
109 const: 0
112 const: 0
121 "^dp-phy@[0-9a-f]+$":
139 const: 0
167 reg = <0x088e9000 0x18c>,
168 <0x088e8000 0x10>,
169 <0x088ea000 0x40>;
174 ranges = <0x0 0x088e9000 0x2000>;
190 reg = <0x200 0x128>,
[all …]
/kernel/linux/linux-5.10/drivers/media/dvb-frontends/
Dmxl5xx_regs.h23 #define HYDRA_INTR_STATUS_REG 0x80030008
24 #define HYDRA_INTR_MASK_REG 0x8003000C
26 #define HYDRA_CRYSTAL_SETTING 0x3FFFC5F0 /* 0 - 24 MHz & 1 - 27 MHz */
27 #define HYDRA_CRYSTAL_CAP 0x3FFFEDA4 /* 0 - 24 MHz & 1 - 27 MHz */
29 #define HYDRA_CPU_RESET_REG 0x8003003C
30 #define HYDRA_CPU_RESET_DATA 0x00000400
32 #define HYDRA_RESET_TRANSPORT_FIFO_REG 0x80030028
33 #define HYDRA_RESET_TRANSPORT_FIFO_DATA 0x00000000
35 #define HYDRA_RESET_BBAND_REG 0x80030024
36 #define HYDRA_RESET_BBAND_DATA 0x00000000
[all …]
Dstv6111.c46 { 2572, 0 },
82 { 1548, 0 },
118 { 4870, 0x3000 },
119 { 4850, 0x3C00 },
120 { 4800, 0x4500 },
121 { 4750, 0x4800 },
122 { 4700, 0x4B00 },
123 { 4650, 0x4D00 },
124 { 4600, 0x4F00 },
125 { 4550, 0x5100 },
[all …]
/kernel/linux/linux-6.6/drivers/media/dvb-frontends/
Dmxl5xx_regs.h13 #define HYDRA_INTR_STATUS_REG 0x80030008
14 #define HYDRA_INTR_MASK_REG 0x8003000C
16 #define HYDRA_CRYSTAL_SETTING 0x3FFFC5F0 /* 0 - 24 MHz & 1 - 27 MHz */
17 #define HYDRA_CRYSTAL_CAP 0x3FFFEDA4 /* 0 - 24 MHz & 1 - 27 MHz */
19 #define HYDRA_CPU_RESET_REG 0x8003003C
20 #define HYDRA_CPU_RESET_DATA 0x00000400
22 #define HYDRA_RESET_TRANSPORT_FIFO_REG 0x80030028
23 #define HYDRA_RESET_TRANSPORT_FIFO_DATA 0x00000000
25 #define HYDRA_RESET_BBAND_REG 0x80030024
26 #define HYDRA_RESET_BBAND_DATA 0x00000000
[all …]
Dstv6111.c37 { 2572, 0 },
73 { 1548, 0 },
109 { 4870, 0x3000 },
110 { 4850, 0x3C00 },
111 { 4800, 0x4500 },
112 { 4750, 0x4800 },
113 { 4700, 0x4B00 },
114 { 4650, 0x4D00 },
115 { 4600, 0x4F00 },
116 { 4550, 0x5100 },
[all …]
/kernel/linux/linux-5.10/arch/c6x/platforms/
Dcache.c16 #define IMCR_CCFG 0x0000
17 #define IMCR_L1PCFG 0x0020
18 #define IMCR_L1PCC 0x0024
19 #define IMCR_L1DCFG 0x0040
20 #define IMCR_L1DCC 0x0044
21 #define IMCR_L2ALLOC0 0x2000
22 #define IMCR_L2ALLOC1 0x2004
23 #define IMCR_L2ALLOC2 0x2008
24 #define IMCR_L2ALLOC3 0x200c
25 #define IMCR_L2WBAR 0x4000
[all …]
/kernel/linux/linux-5.10/drivers/clk/imx/
Dclk-imx7d.c32 { .val = 0, .div = 4, },
40 { .val = 0, .div = 1, },
393 hws[IMX7D_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx7d_clocks_init()
398 base = of_iomap(np, 0); in imx7d_clocks_init()
402 …hws[IMX7D_PLL_ARM_MAIN_SRC] = imx_clk_hw_mux("pll_arm_main_src", base + 0x60, 14, 2, pll_bypass_s… in imx7d_clocks_init()
403 …hws[IMX7D_PLL_DRAM_MAIN_SRC] = imx_clk_hw_mux("pll_dram_main_src", base + 0x70, 14, 2, pll_bypass_… in imx7d_clocks_init()
404 …hws[IMX7D_PLL_SYS_MAIN_SRC] = imx_clk_hw_mux("pll_sys_main_src", base + 0xb0, 14, 2, pll_bypass_s… in imx7d_clocks_init()
405 …hws[IMX7D_PLL_ENET_MAIN_SRC] = imx_clk_hw_mux("pll_enet_main_src", base + 0xe0, 14, 2, pll_bypass_… in imx7d_clocks_init()
406 …hws[IMX7D_PLL_AUDIO_MAIN_SRC] = imx_clk_hw_mux("pll_audio_main_src", base + 0xf0, 14, 2, pll_bypas… in imx7d_clocks_init()
407 …hws[IMX7D_PLL_VIDEO_MAIN_SRC] = imx_clk_hw_mux("pll_video_main_src", base + 0x130, 14, 2, pll_bypa… in imx7d_clocks_init()
[all …]
/kernel/linux/linux-6.6/drivers/clk/imx/
Dclk-imx7d.c32 { .val = 0, .div = 4, },
40 { .val = 0, .div = 1, },
393 hws[IMX7D_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx7d_clocks_init()
398 base = of_iomap(np, 0); in imx7d_clocks_init()
402 …hws[IMX7D_PLL_ARM_MAIN_SRC] = imx_clk_hw_mux("pll_arm_main_src", base + 0x60, 14, 2, pll_bypass_s… in imx7d_clocks_init()
403 …hws[IMX7D_PLL_DRAM_MAIN_SRC] = imx_clk_hw_mux("pll_dram_main_src", base + 0x70, 14, 2, pll_bypass_… in imx7d_clocks_init()
404 …hws[IMX7D_PLL_SYS_MAIN_SRC] = imx_clk_hw_mux("pll_sys_main_src", base + 0xb0, 14, 2, pll_bypass_s… in imx7d_clocks_init()
405 …hws[IMX7D_PLL_ENET_MAIN_SRC] = imx_clk_hw_mux("pll_enet_main_src", base + 0xe0, 14, 2, pll_bypass_… in imx7d_clocks_init()
406 …hws[IMX7D_PLL_AUDIO_MAIN_SRC] = imx_clk_hw_mux("pll_audio_main_src", base + 0xf0, 14, 2, pll_bypas… in imx7d_clocks_init()
407 …hws[IMX7D_PLL_VIDEO_MAIN_SRC] = imx_clk_hw_mux("pll_video_main_src", base + 0x130, 14, 2, pll_bypa… in imx7d_clocks_init()
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/
Di915_reg_defs.h14 * @__n: 0-based bit number
23 ((__n) < 0 || (__n) > 31))))
27 * @__n: 0-based bit number
36 ((__n) < 0 || (__n) > 7))))
40 * @__high: 0-based high bit
41 * @__low: 0-based low bit
51 ((__low) < 0 || (__high) > 31 || (__low) > (__high)))))
55 * @__high: 0-based high bit
56 * @__low: 0-based low bit
66 ((__low) < 0 || (__high) > 63 || (__low) > (__high)))))
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/radeon/
Drv770.c56 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; in rv770_set_uvd_clocks()
71 return 0; in rv770_set_uvd_clocks()
75 43663, 0x03FFFFFE, 1, 30, ~0, in rv770_set_uvd_clocks()
84 /* set UPLL_FB_DIV to 0x50000 */ in rv770_set_uvd_clocks()
85 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(0x50000), ~UPLL_FB_DIV_MASK); in rv770_set_uvd_clocks()
88 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~(UPLL_RESET_MASK | UPLL_SLEEP_MASK)); in rv770_set_uvd_clocks()
90 /* assert BYPASS EN and FB_DIV[0] <- ??? why? */ in rv770_set_uvd_clocks()
117 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); in rv770_set_uvd_clocks()
121 /* deassert BYPASS EN and FB_DIV[0] <- ??? why? */ in rv770_set_uvd_clocks()
122 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK); in rv770_set_uvd_clocks()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/
Drv770.c53 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; in rv770_set_uvd_clocks()
68 return 0; in rv770_set_uvd_clocks()
72 43663, 0x03FFFFFE, 1, 30, ~0, in rv770_set_uvd_clocks()
81 /* set UPLL_FB_DIV to 0x50000 */ in rv770_set_uvd_clocks()
82 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(0x50000), ~UPLL_FB_DIV_MASK); in rv770_set_uvd_clocks()
85 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~(UPLL_RESET_MASK | UPLL_SLEEP_MASK)); in rv770_set_uvd_clocks()
87 /* assert BYPASS EN and FB_DIV[0] <- ??? why? */ in rv770_set_uvd_clocks()
114 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); in rv770_set_uvd_clocks()
118 /* deassert BYPASS EN and FB_DIV[0] <- ??? why? */ in rv770_set_uvd_clocks()
119 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK); in rv770_set_uvd_clocks()
[all …]
/kernel/linux/linux-6.6/arch/mips/include/asm/
Dcpu.h16 register 15, select 0) is defined in this (backwards compatible) way:
24 that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
28 #define PRID_OPT_MASK 0xff000000
34 #define PRID_COMP_MASK 0xff0000
36 #define PRID_COMP_LEGACY 0x000000
37 #define PRID_COMP_MIPS 0x010000
38 #define PRID_COMP_BROADCOM 0x020000
39 #define PRID_COMP_ALCHEMY 0x030000
40 #define PRID_COMP_SIBYTE 0x040000
41 #define PRID_COMP_SANDCRAFT 0x050000
[all …]
/kernel/linux/linux-5.10/arch/mips/include/asm/
Dcpu.h16 register 15, select 0) is defined in this (backwards compatible) way:
24 that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
28 #define PRID_OPT_MASK 0xff000000
34 #define PRID_COMP_MASK 0xff0000
36 #define PRID_COMP_LEGACY 0x000000
37 #define PRID_COMP_MIPS 0x010000
38 #define PRID_COMP_BROADCOM 0x020000
39 #define PRID_COMP_ALCHEMY 0x030000
40 #define PRID_COMP_SIBYTE 0x040000
41 #define PRID_COMP_SANDCRAFT 0x050000
[all …]
/kernel/linux/linux-6.6/drivers/hwmon/
Djc42.c27 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, I2C_CLIENT_END };
30 #define JC42_REG_CAP 0x00
31 #define JC42_REG_CONFIG 0x01
32 #define JC42_REG_TEMP_UPPER 0x02
33 #define JC42_REG_TEMP_LOWER 0x03
34 #define JC42_REG_TEMP_CRITICAL 0x04
35 #define JC42_REG_TEMP 0x05
36 #define JC42_REG_MANID 0x06
37 #define JC42_REG_DEVICEID 0x07
38 #define JC42_REG_SMBUS 0x22 /* NXP and Atmel, possibly others? */
[all …]
/kernel/linux/linux-5.10/drivers/hwmon/
Djc42.c26 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, I2C_CLIENT_END };
29 #define JC42_REG_CAP 0x00
30 #define JC42_REG_CONFIG 0x01
31 #define JC42_REG_TEMP_UPPER 0x02
32 #define JC42_REG_TEMP_LOWER 0x03
33 #define JC42_REG_TEMP_CRITICAL 0x04
34 #define JC42_REG_TEMP 0x05
35 #define JC42_REG_MANID 0x06
36 #define JC42_REG_DEVICEID 0x07
37 #define JC42_REG_SMBUS 0x22 /* NXP and Atmel, possibly others? */
[all …]
/kernel/linux/linux-5.10/tools/testing/selftests/tpm2/
Dtpm2.py12 TPM2_ST_NO_SESSIONS = 0x8001
13 TPM2_ST_SESSIONS = 0x8002
15 TPM2_CC_FIRST = 0x01FF
17 TPM2_CC_CREATE_PRIMARY = 0x0131
18 TPM2_CC_DICTIONARY_ATTACK_LOCK_RESET = 0x0139
19 TPM2_CC_CREATE = 0x0153
20 TPM2_CC_LOAD = 0x0157
21 TPM2_CC_UNSEAL = 0x015E
22 TPM2_CC_FLUSH_CONTEXT = 0x0165
23 TPM2_CC_START_AUTH_SESSION = 0x0176
[all …]
/kernel/linux/linux-6.6/tools/testing/selftests/tpm2/
Dtpm2.py12 TPM2_ST_NO_SESSIONS = 0x8001
13 TPM2_ST_SESSIONS = 0x8002
15 TPM2_CC_FIRST = 0x01FF
17 TPM2_CC_CREATE_PRIMARY = 0x0131
18 TPM2_CC_DICTIONARY_ATTACK_LOCK_RESET = 0x0139
19 TPM2_CC_CREATE = 0x0153
20 TPM2_CC_LOAD = 0x0157
21 TPM2_CC_UNSEAL = 0x015E
22 TPM2_CC_FLUSH_CONTEXT = 0x0165
23 TPM2_CC_START_AUTH_SESSION = 0x0176
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/hisilicon/
Dhip04_eth.c19 #define SC_PPE_RESET_DREQ 0x026C
21 #define PPE_CFG_RX_ADDR 0x100
22 #define PPE_CFG_POOL_GRP 0x300
23 #define PPE_CFG_RX_BUF_SIZE 0x400
24 #define PPE_CFG_RX_FIFO_SIZE 0x500
25 #define PPE_CURR_BUF_CNT 0xa200
27 #define GE_DUPLEX_TYPE 0x08
28 #define GE_MAX_FRM_SIZE_REG 0x3c
29 #define GE_PORT_MODE 0x40
30 #define GE_PORT_EN 0x44
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/hisilicon/
Dhip04_eth.c19 #define SC_PPE_RESET_DREQ 0x026C
21 #define PPE_CFG_RX_ADDR 0x100
22 #define PPE_CFG_POOL_GRP 0x300
23 #define PPE_CFG_RX_BUF_SIZE 0x400
24 #define PPE_CFG_RX_FIFO_SIZE 0x500
25 #define PPE_CURR_BUF_CNT 0xa200
27 #define GE_DUPLEX_TYPE 0x08
28 #define GE_MAX_FRM_SIZE_REG 0x3c
29 #define GE_PORT_MODE 0x40
30 #define GE_PORT_EN 0x44
[all …]

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