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/kernel/linux/linux-5.10/arch/arm/mach-omap1/include/mach/
Domap7xx.h40 #define OMAP7XX_DSP_BASE 0xE0000000
41 #define OMAP7XX_DSP_SIZE 0x50000
42 #define OMAP7XX_DSP_START 0xE0000000
44 #define OMAP7XX_DSPREG_BASE 0xE1000000
46 #define OMAP7XX_DSPREG_START 0xE1000000
48 #define OMAP7XX_SPI1_BASE 0xfffc0800
49 #define OMAP7XX_SPI2_BASE 0xfffc1000
56 #define OMAP7XX_CONFIG_BASE 0xfffe1000
57 #define OMAP7XX_IO_CONF_0 0xfffe1070
58 #define OMAP7XX_IO_CONF_1 0xfffe1074
[all …]
Domap1510.h38 #define OMAP1510_DSP_BASE 0xE0000000
39 #define OMAP1510_DSP_SIZE 0x28000
40 #define OMAP1510_DSP_START 0xE0000000
42 #define OMAP1510_DSPREG_BASE 0xE1000000
44 #define OMAP1510_DSPREG_START 0xE1000000
46 #define OMAP1510_DSP_MMU_BASE (0xfffed200)
53 #define OMAP1510_FPGA_BASE 0xE8000000 /* VA */
55 #define OMAP1510_FPGA_START 0x08000000 /* PA */
58 #define OMAP1510_FPGA_REV_LOW IOMEM(OMAP1510_FPGA_BASE + 0x0)
59 #define OMAP1510_FPGA_REV_HIGH IOMEM(OMAP1510_FPGA_BASE + 0x1)
[all …]
Domap16xx.h38 #define OMAP16XX_DSP_BASE 0xE0000000
39 #define OMAP16XX_DSP_SIZE 0x28000
40 #define OMAP16XX_DSP_START 0xE0000000
42 #define OMAP16XX_DSPREG_BASE 0xE1000000
44 #define OMAP16XX_DSPREG_START 0xE1000000
46 #define OMAP16XX_SEC_BASE 0xFFFE4000
47 #define OMAP16XX_SEC_DES (OMAP16XX_SEC_BASE + 0x0000)
48 #define OMAP16XX_SEC_SHA1MD5 (OMAP16XX_SEC_BASE + 0x0800)
49 #define OMAP16XX_SEC_RNG (OMAP16XX_SEC_BASE + 0x1000)
56 #define OMAP_IH2_0_BASE (0xfffe0000)
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/memory-controllers/
Dpl353-smc.txt28 reg = <0xe000e000 0x1000>;
31 ranges = <0x0 0x0 0xe1000000 0x1000000 //Nand CS Region
32 0x1 0x0 0xe2000000 0x2000000 //SRAM/NOR CS Region
33 0x2 0x0 0xe4000000 0x2000000>; //SRAM/NOR CS Region
36 reg = <0 0 0x1000000>;
41 reg = <1 0 0x2000000>;
45 reg = <2 0 0x2000000>;
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/mtd/
Darm,pl353-nand-r2p1.yaml37 reg = <0xe000e000 0x0001000>;
40 ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */
41 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */
42 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */
46 nfc0: nand-controller@0,0 {
48 reg = <0 0 0x1000000>;
50 #size-cells = <0>;
Dintel,lgm-ebunand.yaml48 minimum: 0
70 reg = <0xe0f00000 0x100>,
71 <0xe1000000 0x300>,
72 <0xe1400000 0x8000>,
73 <0xe1c00000 0x1000>,
74 <0x17400000 0x4>,
75 <0x17c00000 0x4>;
82 #size-cells = <0>;
84 nand@0 {
85 reg = <0>;
/kernel/linux/linux-6.6/tools/testing/selftests/arm64/fp/
Dsme-inst.h12 .inst 0x4bf5800 \
33 .macro _ldr_za nw, nxbase, offset=0
34 .inst 0xe1000000 \
44 .macro _str_za nw, nxbase, offset=0
45 .inst 0xe1200000 \
57 .inst 0xe11f8000 \
58 | (((\nx) & 0x1f) << 5)
67 .inst 0xe13f8000 \
68 | (((\nx) & 0x1f) << 5)
/kernel/linux/linux-5.10/include/video/
Dcvisionppc.h27 #define CSPPC_PCI_BRIDGE 0xfffe0000
28 #define CSPPC_BRIDGE_ENDIAN 0x0000
29 #define CSPPC_BRIDGE_INT 0x0010
31 #define CVPPC_PCI_CONFIG 0xfffc0000
32 #define CVPPC_ROM_ADDRESS 0xe2000001
33 #define CVPPC_REGS_REGION 0xef000000
34 #define CVPPC_FB_APERTURE_ONE 0xe0000000
35 #define CVPPC_FB_APERTURE_TWO 0xe1000000
36 #define CVPPC_FB_SIZE 0x00800000
37 #define CVPPC_MEM_CONFIG_OLD 0xed61fcaa /* FIXME Fujitsu?? */
[all …]
/kernel/linux/linux-6.6/include/video/
Dcvisionppc.h27 #define CSPPC_PCI_BRIDGE 0xfffe0000
28 #define CSPPC_BRIDGE_ENDIAN 0x0000
29 #define CSPPC_BRIDGE_INT 0x0010
31 #define CVPPC_PCI_CONFIG 0xfffc0000
32 #define CVPPC_ROM_ADDRESS 0xe2000001
33 #define CVPPC_REGS_REGION 0xef000000
34 #define CVPPC_FB_APERTURE_ONE 0xe0000000
35 #define CVPPC_FB_APERTURE_TWO 0xe1000000
36 #define CVPPC_FB_SIZE 0x00800000
37 #define CVPPC_MEM_CONFIG_OLD 0xed61fcaa /* FIXME Fujitsu?? */
[all …]
/kernel/linux/linux-5.10/arch/powerpc/boot/dts/fsl/
Dmpc8544ds.dts16 reg = <0 0 0 0>; // Filled by U-Boot
20 reg = <0 0xe0005000 0 0x1000>;
22 ranges = <0x0 0x0 0x0 0xff800000 0x800000>;
26 ranges = <0x0 0x0 0xe0000000 0x100000>;
30 reg = <0 0xe0008000 0 0x1000>;
31 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
32 0x1000000 0x0 0x00000000 0 0xe1000000 0x0 0x10000>;
34 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
37 /* IDSEL 0x11 J17 Slot 1 */
38 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
[all …]
/kernel/linux/linux-6.6/arch/powerpc/boot/dts/fsl/
Dmpc8544ds.dts16 reg = <0 0 0 0>; // Filled by U-Boot
20 reg = <0 0xe0005000 0 0x1000>;
22 ranges = <0x0 0x0 0x0 0xff800000 0x800000>;
26 ranges = <0x0 0x0 0xe0000000 0x100000>;
30 reg = <0 0xe0008000 0 0x1000>;
31 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
32 0x1000000 0x0 0x00000000 0 0xe1000000 0x0 0x10000>;
34 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
37 /* IDSEL 0x11 J17 Slot 1 */
38 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/memory-controllers/
Darm,pl35x-smc.yaml33 pattern: "^memory-controller@[0-9a-f]+$"
69 - description: Combined or Memory interface 0 IRQ
73 "@[0-7],[a-f0-9]+$":
91 minimum: 0
141 reg = <0xe000e000 0x0001000>;
144 ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */
145 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */
146 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */
150 nfc0: nand-controller@0,0 {
152 reg = <0 0 0x1000000>;
[all …]
/kernel/linux/linux-6.6/arch/arm/mach-omap1/
Dhardware.h53 ? OMAP_CS3_PHYS : 0; in omap_cs0m_phys()
59 ? 0 : OMAP_CS3_PHYS; in omap_cs3_phys()
64 #define OMAP1_IO_OFFSET 0x00f00000 /* Virtual IO = 0xff0b0000 */
82 #define OMAP_MPU_TIMER1_BASE (0xfffec500)
83 #define OMAP_MPU_TIMER2_BASE (0xfffec600)
84 #define OMAP_MPU_TIMER3_BASE (0xfffec700)
88 #define MPU_TIMER_ST (1 << 0)
97 #define OMAP_MPU_WATCHDOG_BASE (0xfffec800)
98 #define OMAP_WDT_TIMER (OMAP_MPU_WATCHDOG_BASE + 0x0)
99 #define OMAP_WDT_LOAD_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4)
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/amd/
Damd-seattle-soc.dtsi20 reg = <0x0 0xe1110000 0 0x1000>,
21 <0x0 0xe112f000 0 0x2000>,
22 <0x0 0xe1140000 0 0x2000>,
23 <0x0 0xe1160000 0 0x2000>;
24 interrupts = <1 9 0xf04>;
25 ranges = <0 0 0 0xe1100000 0 0x100000>;
29 reg = <0x0 0x00080000 0 0x1000>;
35 interrupts = <1 13 0xff04>,
36 <1 14 0xff04>,
37 <1 11 0xff04>,
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/qcom/
Dsm8350-sony-xperia-sagami.dtsi33 reg = <0 0xe1000000 0 0x2300000>;
53 pinctrl-0 = <&focus_n &snapshot_n &vol_down_n &g_assist_n>;
94 reg = <0 0xe1000000 0 0x2300000>;
100 reg = <0 0xffc00000 0 0x100000>;
101 console-size = <0x40000>;
102 record-size = <0x1000>;
124 regulators-0 {
496 reg = <0x40>;
511 reg = <0x41>;
592 power-source = <0>;
[all …]
/kernel/linux/linux-6.6/arch/powerpc/boot/dts/
Dcurrituck.dts13 /memreserve/ 0x01f00000 0x00100000; // spin table
20 dcr-parent = <&{/cpus/cpu@0}>;
28 #size-cells = <0>;
30 cpu@0 {
33 reg = <0>;
58 cpu-release-addr = <0x0 0x01f00000>;
64 reg = <0x0 0x0 0x0 0x0>; // filled in by zImage
70 dcr-reg = <0xffc00000 0x00040000>;
71 #address-cells = <0>;
72 #size-cells = <0>;
[all …]
/kernel/linux/linux-5.10/arch/powerpc/boot/dts/
Dcurrituck.dts13 /memreserve/ 0x01f00000 0x00100000; // spin table
20 dcr-parent = <&{/cpus/cpu@0}>;
28 #size-cells = <0>;
30 cpu@0 {
33 reg = <0>;
58 cpu-release-addr = <0x0 0x01f00000>;
64 reg = <0x0 0x0 0x0 0x0>; // filled in by zImage
70 dcr-reg = <0xffc00000 0x00040000>;
71 #address-cells = <0>;
72 #size-cells = <0>;
[all …]
Dmpc8610_hpcd.dts26 #size-cells = <0>;
28 PowerPC,8610@0 {
30 reg = <0>;
35 sleep = <&pmc 0x00008000 0 // core
36 &pmc 0x00004000 0>; // timebase
37 timebase-frequency = <0>; // From uboot
38 bus-frequency = <0>; // From uboot
39 clock-frequency = <0>; // From uboot
45 reg = <0x00000000 0x20000000>; // 512M at 0x0
52 reg = <0xe0005000 0x1000>;
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/amd/
Damd-seattle-soc.dtsi20 reg = <0x0 0xe1110000 0 0x1000>,
21 <0x0 0xe112f000 0 0x2000>,
22 <0x0 0xe1140000 0 0x2000>,
23 <0x0 0xe1160000 0 0x2000>;
24 interrupts = <1 9 0xf04>;
25 ranges = <0 0 0 0xe1100000 0 0x100000>;
29 reg = <0x0 0x00080000 0 0x1000>;
35 interrupts = <1 13 0xff04>,
36 <1 14 0xff04>,
37 <1 11 0xff04>,
[all …]
/kernel/linux/linux-6.6/arch/arm64/include/asm/
Dfpsimdmacros.h12 stp q0, q1, [\state, #16 * 0]
48 ldp q0, q1, [\state, #16 * 0]
73 .if (\nr) < 0 || (\nr) > 30
79 .if (\znr) < 0 || (\znr) > 31
85 .if (\pnr) < 0 || (\pnr) > 15
106 .macro _sve_str_v nz, nxbase, offset=0
109 _check_num (\offset), -0x100, 0xff
110 .inst 0xe5804000 \
114 | (((\offset) & 0x1f8) << 13)
118 .macro _sve_ldr_v nz, nxbase, offset=0
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dlpc32xx.dtsi20 #size-cells = <0>;
22 cpu@0 {
25 reg = <0x0>;
32 #clock-cells = <0>;
39 #clock-cells = <0>;
49 ranges = <0x00000000 0x00000000 0x10000000>,
50 <0x20000000 0x20000000 0x30000000>,
51 <0xe0000000 0xe0000000 0x04000000>;
55 reg = <0x08000000 0x20000>;
59 ranges = <0x00000000 0x08000000 0x20000>;
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/nxp/lpc/
Dlpc32xx.dtsi20 #size-cells = <0>;
22 cpu@0 {
25 reg = <0x0>;
32 #clock-cells = <0>;
39 #clock-cells = <0>;
49 ranges = <0x00000000 0x00000000 0x10000000>,
50 <0x20000000 0x20000000 0x30000000>,
51 <0xe0000000 0xe0000000 0x04000000>;
55 reg = <0x08000000 0x20000>;
59 ranges = <0x00000000 0x08000000 0x20000>;
[all …]
/kernel/linux/linux-6.6/tools/testing/selftests/arm64/abi/
Dsyscall-abi-asm.S11 // x0: SVE VL, 0 for FP only
33 .macro _ldr_za nw, nxbase, offset=0
34 .inst 0xe1000000 \
44 .macro _str_za nw, nxbase, offset=0
45 .inst 0xe1200000 \
57 .inst 0xe11f8000 \
58 | (((\nx) & 0x1f) << 5)
67 .inst 0xe13f8000 \
68 | (((\nx) & 0x1f) << 5)
92 mov w12, #0
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/xilinx/
Dzynq-7000.dtsi13 #size-cells = <0>;
15 cpu0: cpu@0 {
18 reg = <0>;
47 interrupts = <0 5 4>, <0 6 4>;
49 reg = <0xf8891000 0x1000>,
50 <0xf8893000 0x1000>;
69 #size-cells = <0>;
72 port@0 {
73 reg = <0>;
104 reg = <0xf8007100 0x20>;
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-cns3xxx/
Dcns3xxx.h12 #define CNS3XXX_FLASH_BASE 0x10000000 /* Flash/SRAM Memory Bank 0 */
15 #define CNS3XXX_DDR2SDRAM_BASE 0x20000000 /* DDR2 SDRAM Memory */
17 #define CNS3XXX_SPI_FLASH_BASE 0x60000000 /* SPI Serial Flash Memory */
19 #define CNS3XXX_SWITCH_BASE 0x70000000 /* Switch and HNAT Control */
21 #define CNS3XXX_PPE_BASE 0x70001000 /* HANT */
23 #define CNS3XXX_EMBEDDED_SRAM_BASE 0x70002000 /* HANT Embedded SRAM */
25 #define CNS3XXX_SSP_BASE 0x71000000 /* Synchronous Serial Port - SPI/PCM/I2C */
27 #define CNS3XXX_DMC_BASE 0x72000000 /* DMC Control (DDR2 SDRAM) */
29 #define CNS3XXX_SMC_BASE 0x73000000 /* SMC Control */
31 #define SMC_MEMC_STATUS_OFFSET 0x000
[all …]

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