Searched +full:0 +full:xf0000 (Results 1 – 25 of 336) sorted by relevance
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27 #define MM_INDEX__MM_OFFSET_MASK 0x7fffffff28 #define MM_INDEX__MM_OFFSET__SHIFT 0x029 #define MM_INDEX__MM_APER_MASK 0x8000000030 #define MM_INDEX__MM_APER__SHIFT 0x1f31 #define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff32 #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x033 #define MM_DATA__MM_DATA_MASK 0xffffffff34 #define MM_DATA__MM_DATA__SHIFT 0x035 #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x236 #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1[all …]
27 #define IH_VMID_0_LUT__PASID_MASK 0xffff28 #define IH_VMID_0_LUT__PASID__SHIFT 0x029 #define IH_VMID_1_LUT__PASID_MASK 0xffff30 #define IH_VMID_1_LUT__PASID__SHIFT 0x031 #define IH_VMID_2_LUT__PASID_MASK 0xffff32 #define IH_VMID_2_LUT__PASID__SHIFT 0x033 #define IH_VMID_3_LUT__PASID_MASK 0xffff34 #define IH_VMID_3_LUT__PASID__SHIFT 0x035 #define IH_VMID_4_LUT__PASID_MASK 0xffff36 #define IH_VMID_4_LUT__PASID__SHIFT 0x0[all …]
23 #define TPC0_QM_GLBL_CFG0_PQF_EN_SHIFT 024 #define TPC0_QM_GLBL_CFG0_PQF_EN_MASK 0xF26 #define TPC0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F028 #define TPC0_QM_GLBL_CFG0_CP_EN_MASK 0x3E0031 #define TPC0_QM_GLBL_CFG1_PQF_STOP_SHIFT 032 #define TPC0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF34 #define TPC0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F036 #define TPC0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E0038 #define TPC0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF000040 #define TPC0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000[all …]
23 #define DMA0_QM_GLBL_CFG0_PQF_EN_SHIFT 024 #define DMA0_QM_GLBL_CFG0_PQF_EN_MASK 0xF26 #define DMA0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F028 #define DMA0_QM_GLBL_CFG0_CP_EN_MASK 0x3E0031 #define DMA0_QM_GLBL_CFG1_PQF_STOP_SHIFT 032 #define DMA0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF34 #define DMA0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F036 #define DMA0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E0038 #define DMA0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF000040 #define DMA0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000[all …]
23 #define MME0_QM_GLBL_CFG0_PQF_EN_SHIFT 024 #define MME0_QM_GLBL_CFG0_PQF_EN_MASK 0xF26 #define MME0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F028 #define MME0_QM_GLBL_CFG0_CP_EN_MASK 0x3E0031 #define MME0_QM_GLBL_CFG1_PQF_STOP_SHIFT 032 #define MME0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF34 #define MME0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F036 #define MME0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E0038 #define MME0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF000040 #define MME0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000[all …]
23 #define NIC0_QM0_GLBL_CFG0_PQF_EN_SHIFT 024 #define NIC0_QM0_GLBL_CFG0_PQF_EN_MASK 0xF26 #define NIC0_QM0_GLBL_CFG0_CQF_EN_MASK 0x1F028 #define NIC0_QM0_GLBL_CFG0_CP_EN_MASK 0x3E0031 #define NIC0_QM0_GLBL_CFG1_PQF_STOP_SHIFT 032 #define NIC0_QM0_GLBL_CFG1_PQF_STOP_MASK 0xF34 #define NIC0_QM0_GLBL_CFG1_CQF_STOP_MASK 0x1F036 #define NIC0_QM0_GLBL_CFG1_CP_STOP_MASK 0x3E0038 #define NIC0_QM0_GLBL_CFG1_PQF_FLUSH_MASK 0xF000040 #define NIC0_QM0_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000[all …]
23 memory@0 {25 reg = <0x00000000 0x00000000 0x00000000 0x20000000>;35 gpios-states = <0>;36 states = <1800000 0x137 3300000 0x0>;81 flash@0 {82 reg = <0>;91 partition@0 {93 reg = <0 0xf0000>;98 reg = <0xf0000 0x8000>;[all …]
11 #define RF_DATA 0x1d413 #define rPMAC_Reset 0x10014 #define rPMAC_TxStart 0x10415 #define rPMAC_TxLegacySIG 0x10816 #define rPMAC_TxHTSIG1 0x10c17 #define rPMAC_TxHTSIG2 0x11018 #define rPMAC_PHYDebug 0x11419 #define rPMAC_TxPacketNum 0x11820 #define rPMAC_TxIdle 0x11c21 #define rPMAC_TxMACHeader0 0x120[all …]
10 #define RF_DATA 0x1d412 #define rPMAC_Reset 0x10013 #define rPMAC_TxStart 0x10414 #define rPMAC_TxLegacySIG 0x10815 #define rPMAC_TxHTSIG1 0x10c16 #define rPMAC_TxHTSIG2 0x11017 #define rPMAC_PHYDebug 0x11418 #define rPMAC_TxPacketNum 0x11819 #define rPMAC_TxIdle 0x11c20 #define rPMAC_TxMACHeader0 0x120[all …]
24 #define PDMA0_QM_GLBL_CFG0_PQF_EN_SHIFT 025 #define PDMA0_QM_GLBL_CFG0_PQF_EN_MASK 0xF27 #define PDMA0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F029 #define PDMA0_QM_GLBL_CFG0_CP_EN_MASK 0x3E0031 #define PDMA0_QM_GLBL_CFG0_ARC_CQF_EN_MASK 0x400034 #define PDMA0_QM_GLBL_CFG1_PQF_STOP_SHIFT 035 #define PDMA0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF37 #define PDMA0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F039 #define PDMA0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E0041 #define PDMA0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000[all …]
24 #define DCORE0_EDMA0_QM_GLBL_CFG0_PQF_EN_SHIFT 025 #define DCORE0_EDMA0_QM_GLBL_CFG0_PQF_EN_MASK 0xF27 #define DCORE0_EDMA0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F029 #define DCORE0_EDMA0_QM_GLBL_CFG0_CP_EN_MASK 0x3E0031 #define DCORE0_EDMA0_QM_GLBL_CFG0_ARC_CQF_EN_MASK 0x400034 #define DCORE0_EDMA0_QM_GLBL_CFG1_PQF_STOP_SHIFT 035 #define DCORE0_EDMA0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF37 #define DCORE0_EDMA0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F039 #define DCORE0_EDMA0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E0041 #define DCORE0_EDMA0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000[all …]
27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x128 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x029 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x230 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x131 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x432 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x233 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x834 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x335 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x1036 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4[all …]
14 #define CCSC00_OFFSET 0xAA05015 #define CCSC01_OFFSET 0xFA05016 #define CCSC10_OFFSET 0xA000017 #define CCSC11_OFFSET 0xF000019 #define SUN8I_CSC_CTRL(base) ((base) + 0x0)20 #define SUN8I_CSC_COEFF(base, i) ((base) + 0x10 + 4 * (i))22 #define SUN8I_CSC_CTRL_EN BIT(0)