| /kernel/linux/linux-5.10/Documentation/filesystems/ext4/ |
| D | blocks.rst | 7 sectors between 1KiB and 64KiB, and the number of sectors must be an
10 4KiB. You may experience mounting problems if block size is greater than
11 page size (i.e. 64KiB blocks on a i386 which only has 4KiB memory
20 :widths: 1 1 1 1 1
21 :header-rows: 1
24 - 1KiB
25 - 2KiB
26 - 4KiB
27 - 64KiB
66 - 1,074,791,436
[all …]
|
| /kernel/linux/linux-6.6/Documentation/filesystems/ext4/ |
| D | blocks.rst | 7 sectors between 1KiB and 64KiB, and the number of sectors must be an
10 4KiB. You may experience mounting problems if block size is greater than
11 page size (i.e. 64KiB blocks on a i386 which only has 4KiB memory
20 :widths: 1 1 1 1 1
21 :header-rows: 1
24 - 1KiB
25 - 2KiB
26 - 4KiB
27 - 64KiB
66 - 1,074,791,436
[all …]
|
| /kernel/linux/linux-6.6/arch/x86/platform/intel-quark/ |
| D | imr_selftest.c | 56 * zero sized allocations and 1 KiB sized areas.
84 /* Test that a 1 KiB IMR @ zero with read/write all will bomb out. */ in imr_self_test()
87 imr_self_test_result(ret < 0, "1KiB IMR @ 0x00000000 - access-all\n"); in imr_self_test()
89 /* Test that a 1 KiB IMR @ zero with CPU only will work. */ in imr_self_test()
91 imr_self_test_result(ret >= 0, "1KiB IMR @ 0x00000000 - cpu-access\n"); in imr_self_test()
97 /* Test 2 KiB works. */ in imr_self_test()
100 imr_self_test_result(ret >= 0, "2KiB IMR @ 0x00000000\n"); in imr_self_test()
103 imr_self_test_result(ret == 0, "teardown 2KiB\n"); in imr_self_test()
|
| D | imr.c | 56 * 23:2 1 KiB aligned lo address
57 * 1:0 Reserved
61 * 23:2 1 KiB aligned hi address
62 * 1:0 Reserved
213 size = end - base + 1; in imr_dbgfs_state_show()
252 pr_err("base %pa size 0x%08zx must align to 1KiB\n", in imr_check_params()
292 * @base: physical base address of region aligned to 1KiB.
293 * @size: physical size of region in bytes must be aligned to 1KiB.
339 reg = -1; in imr_add_range()
358 if (reg == -1) { in imr_add_range()
[all …]
|
| /kernel/linux/linux-5.10/arch/x86/platform/intel-quark/ |
| D | imr_selftest.c | 56 * zero sized allocations and 1 KiB sized areas.
84 /* Test that a 1 KiB IMR @ zero with read/write all will bomb out. */ in imr_self_test()
87 imr_self_test_result(ret < 0, "1KiB IMR @ 0x00000000 - access-all\n"); in imr_self_test()
89 /* Test that a 1 KiB IMR @ zero with CPU only will work. */ in imr_self_test()
91 imr_self_test_result(ret >= 0, "1KiB IMR @ 0x00000000 - cpu-access\n"); in imr_self_test()
97 /* Test 2 KiB works. */ in imr_self_test()
100 imr_self_test_result(ret >= 0, "2KiB IMR @ 0x00000000\n"); in imr_self_test()
103 imr_self_test_result(ret == 0, "teardown 2KiB\n"); in imr_self_test()
|
| D | imr.c | 56 * 23:2 1 KiB aligned lo address
57 * 1:0 Reserved
61 * 23:2 1 KiB aligned hi address
62 * 1:0 Reserved
213 size = end - base + 1; in imr_dbgfs_state_show()
252 pr_err("base %pa size 0x%08zx must align to 1KiB\n", in imr_check_params()
292 * @base: physical base address of region aligned to 1KiB.
293 * @size: physical size of region in bytes must be aligned to 1KiB.
339 reg = -1; in imr_add_range()
358 if (reg == -1) { in imr_add_range()
[all …]
|
| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | bcm2837.dtsi | 32 <1 IRQ_TYPE_LEVEL_HIGH>, // PHYS_NONSECURE_PPI
39 #address-cells = <1>;
44 * https://developer.arm.com/documentation/ddi0500/e/level-1-memory-system
58 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
61 i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
65 cpu1: cpu@1 {
68 reg = <1>;
73 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
76 i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
88 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
[all …]
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| D | armada-385-linksys-rango.dts | 25 wan_white@1 {
86 #address-cells = <1>;
87 #size-cells = <1>;
97 reg = <0x200000 0x20000>; /* 128KiB */
102 reg = <0x220000 0x40000>; /* 256KiB */
107 reg = <0x7e0000 0x40000>; /* 256KiB */
113 reg = <0x820000 0x1e0000>; /* 1920KiB */
163 no-1-8-v;
|
| /kernel/linux/linux-6.6/arch/arm/boot/dts/broadcom/ |
| D | bcm2837.dtsi | 31 <1 IRQ_TYPE_LEVEL_HIGH>, // PHYS_NONSECURE_PPI
38 #address-cells = <1>;
43 * https://developer.arm.com/documentation/ddi0500/e/level-1-memory-system
57 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
60 i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
64 cpu1: cpu@1 {
67 reg = <1>;
72 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
75 i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
87 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
[all …]
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| D | bcm2836.dtsi | 32 <1 IRQ_TYPE_LEVEL_HIGH>, // PHYS_NONSECURE_PPI
39 #address-cells = <1>;
58 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
61 i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
65 v7_cpu1: cpu@1 {
72 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
75 i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
86 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
89 i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
100 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
[all …]
|
| /kernel/linux/linux-6.6/Documentation/arch/arm/ |
| D | tcm.rst | 8 This is usually just a few (4-64) KiB of RAM inside the ARM
15 The size of DTCM or ITCM is minimum 4KiB so the typical
16 minimum configuration is 4KiB ITCM and 4KiB DTCM.
24 determine if ITCM (bits 1-0) and/or DTCM (bit 17-16) is present
39 implementation will map the TCM 1 to 1 from physical to virtual
42 on, supporting a maximum of 32KiB of ITCM and 32KiB of DTCM.
45 TCMs in two separate banks, so for example an 8KiB ITCM is divided
46 into two 4KiB banks with its own control registers. The idea is to
153 tcmem[1] = 0x2BADBABEU;
|
| /kernel/linux/linux-5.10/Documentation/arm/ |
| D | tcm.rst | 8 This is usually just a few (4-64) KiB of RAM inside the ARM
15 The size of DTCM or ITCM is minimum 4KiB so the typical
16 minimum configuration is 4KiB ITCM and 4KiB DTCM.
24 determine if ITCM (bits 1-0) and/or DTCM (bit 17-16) is present
39 implementation will map the TCM 1 to 1 from physical to virtual
42 on, supporting a maximum of 32KiB of ITCM and 32KiB of DTCM.
45 TCMs in two separate banks, so for example an 8KiB ITCM is divided
46 into two 4KiB banks with its own control registers. The idea is to
153 tcmem[1] = 0x2BADBABEU;
|
| /kernel/linux/linux-6.6/Documentation/admin-guide/device-mapper/ |
| D | dm-ebs.rst | 30 1, 2, 4, 8 sectors of 512 bytes supported.
36 2^N supported, e.g. 8 = emulate 8 sectors of 512 bytes = 4KiB.
42 Emulate 1 sector = 512 bytes logical block size on /dev/sda starting at
45 ebs /dev/sda 1024 1
47 Emulate 2 sector = 1KiB logical block size on /dev/sda starting at
48 offset 128 sectors, enforce 2KiB underlying device block size.
49 This presumes 2KiB logical blocksize on /dev/sda or less to work:
|
| /kernel/linux/linux-5.10/Documentation/admin-guide/device-mapper/ |
| D | dm-ebs.rst | 30 1, 2, 4, 8 sectors of 512 bytes supported.
36 2^N supported, e.g. 8 = emulate 8 sectors of 512 bytes = 4KiB.
42 Emulate 1 sector = 512 bytes logical block size on /dev/sda starting at
45 ebs /dev/sda 1024 1
47 Emulate 2 sector = 1KiB logical block size on /dev/sda starting at
48 offset 128 sectors, enforce 2KiB underlying device block size.
49 This presumes 2KiB logical blocksize on /dev/sda or less to work:
|
| /kernel/linux/linux-6.6/Documentation/networking/ |
| D | smc-sysctl.rst | 18 the under device in 1 single sending. If set to 0, the SMC auto corking
34 - 1 - Use virtually contiguous buffers
47 The default value inherits from net.ipv4.tcp_wmem[1].
49 The minimum value is 16KiB and there is no hard limit for max value, but
50 only allowed 512KiB for SMC-R and 1MiB for SMC-D.
56 The default value inherits from net.ipv4.tcp_rmem[1].
58 The minimum value is 16KiB and there is no hard limit for max value, but
59 only allowed 512KiB for SMC-R and 1MiB for SMC-D.
|
| /kernel/linux/linux-6.6/Documentation/gpu/ |
| D | drm-usage-stats.rst | 12 feasible `top(1)` like userspace monitoring tools.
34 1. Mandatory, fully standardised.
67 duplicated and shared file descriptors. Conceptually the value should map 1:1
127 - drm-memory-<region>: <uint> [KiB|MiB]
136 Default unit shall be bytes with optional unit specifiers of 'KiB' or 'MiB'
139 - drm-shared-<region>: <uint> [KiB|MiB]
144 - drm-total-<region>: <uint> [KiB|MiB]
148 - drm-resident-<region>: <uint> [KiB|MiB]
152 - drm-purgeable-<region>: <uint> [KiB|MiB]
156 - drm-active-<region>: <uint> [KiB|MiB]
|
| /kernel/linux/linux-6.6/tools/perf/arch/arm64/util/ |
| D | arm-spe.c | 28 #define KiB(x) ((x) * 1024) macro
73 * snapshot size is specified, then the default is 4MiB for privileged users, 128KiB for in arm_spe_snapshot_resolve_auxtrace_defaults()
76 * The default auxtrace mmap size is 4MiB/page_size for privileged users, 128KiB for in arm_spe_snapshot_resolve_auxtrace_defaults()
78 * will be reduced from the default 512KiB/page_size to 256KiB/page_size, otherwise the in arm_spe_snapshot_resolve_auxtrace_defaults()
89 opts->auxtrace_mmap_pages = KiB(128) / page_size; in arm_spe_snapshot_resolve_auxtrace_defaults()
91 opts->mmap_pages = KiB(256) / page_size; in arm_spe_snapshot_resolve_auxtrace_defaults()
94 opts->mmap_pages = KiB(256) / page_size; in arm_spe_snapshot_resolve_auxtrace_defaults()
125 bool privileged = perf_event_paranoid_check(-1); in arm_spe_recording_options()
184 opts->auxtrace_mmap_pages = KiB(128) / page_size; in arm_spe_recording_options()
186 opts->mmap_pages = KiB(256) / page_size; in arm_spe_recording_options()
[all …]
|
| D | hisi-ptt.c | 27 #define KiB(x) ((x) * 1024) macro
66 bool privileged = perf_event_paranoid_check(-1); in hisi_ptt_set_auxtrace_mmap_page()
75 opts->auxtrace_mmap_pages = KiB(128) / page_size; in hisi_ptt_set_auxtrace_mmap_page()
77 opts->mmap_pages = KiB(256) / page_size; in hisi_ptt_set_auxtrace_mmap_page()
84 size_t min_sz = KiB(8); in hisi_ptt_set_auxtrace_mmap_page()
115 evsel->core.attr.sample_period = 1; in hisi_ptt_recording_options()
141 tracking_evsel->core.attr.sample_period = 1; in hisi_ptt_recording_options()
|
| /kernel/linux/linux-5.10/tools/perf/arch/x86/util/ |
| D | intel-bts.c | 28 #define KiB(x) ((x) * 1024) macro
30 #define KiB_MASK(x) (KiB(x) - 1)
31 #define MiB_MASK(x) (MiB(x) - 1)
114 bool privileged = perf_event_paranoid_check(-1); in intel_bts_recording_options()
131 evsel->core.attr.sample_period = 1; in intel_bts_recording_options()
156 opts->auxtrace_mmap_pages = KiB(128) / page_size; in intel_bts_recording_options()
158 opts->mmap_pages = KiB(256) / page_size; in intel_bts_recording_options()
162 opts->mmap_pages = KiB(256) / page_size; in intel_bts_recording_options()
193 opts->auxtrace_mmap_pages = KiB(128) / page_size; in intel_bts_recording_options()
195 opts->mmap_pages = KiB(256) / page_size; in intel_bts_recording_options()
[all …]
|
| /kernel/linux/linux-6.6/tools/perf/arch/x86/util/ |
| D | intel-bts.c | 28 #define KiB(x) ((x) * 1024) macro
30 #define KiB_MASK(x) (KiB(x) - 1)
31 #define MiB_MASK(x) (MiB(x) - 1)
114 bool privileged = perf_event_paranoid_check(-1); in intel_bts_recording_options()
131 evsel->core.attr.sample_period = 1; in intel_bts_recording_options()
157 opts->auxtrace_mmap_pages = KiB(128) / page_size; in intel_bts_recording_options()
159 opts->mmap_pages = KiB(256) / page_size; in intel_bts_recording_options()
163 opts->mmap_pages = KiB(256) / page_size; in intel_bts_recording_options()
194 opts->auxtrace_mmap_pages = KiB(128) / page_size; in intel_bts_recording_options()
196 opts->mmap_pages = KiB(256) / page_size; in intel_bts_recording_options()
[all …]
|
| /kernel/linux/linux-6.6/drivers/mtd/tests/ |
| D | speedtest.c | 200 if (mtd->writesize == 1) { in mtd_speedtest_init()
243 /* Write all eraseblocks, 1 eraseblock at a time */ in mtd_speedtest_init()
259 pr_info("eraseblock write speed is %ld KiB/s\n", speed); in mtd_speedtest_init()
261 /* Read all eraseblocks, 1 eraseblock at a time */ in mtd_speedtest_init()
277 pr_info("eraseblock read speed is %ld KiB/s\n", speed); in mtd_speedtest_init()
283 /* Write all eraseblocks, 1 page at a time */ in mtd_speedtest_init()
299 pr_info("page write speed is %ld KiB/s\n", speed); in mtd_speedtest_init()
301 /* Read all eraseblocks, 1 page at a time */ in mtd_speedtest_init()
317 pr_info("page read speed is %ld KiB/s\n", speed); in mtd_speedtest_init()
339 pr_info("2 page write speed is %ld KiB/s\n", speed); in mtd_speedtest_init()
[all …]
|
| /kernel/linux/linux-5.10/drivers/mtd/tests/ |
| D | speedtest.c | 201 if (mtd->writesize == 1) { in mtd_speedtest_init()
244 /* Write all eraseblocks, 1 eraseblock at a time */ in mtd_speedtest_init()
260 pr_info("eraseblock write speed is %ld KiB/s\n", speed); in mtd_speedtest_init()
262 /* Read all eraseblocks, 1 eraseblock at a time */ in mtd_speedtest_init()
278 pr_info("eraseblock read speed is %ld KiB/s\n", speed); in mtd_speedtest_init()
284 /* Write all eraseblocks, 1 page at a time */ in mtd_speedtest_init()
300 pr_info("page write speed is %ld KiB/s\n", speed); in mtd_speedtest_init()
302 /* Read all eraseblocks, 1 page at a time */ in mtd_speedtest_init()
318 pr_info("page read speed is %ld KiB/s\n", speed); in mtd_speedtest_init()
340 pr_info("2 page write speed is %ld KiB/s\n", speed); in mtd_speedtest_init()
[all …]
|
| /kernel/linux/linux-6.6/arch/arm/boot/dts/marvell/ |
| D | armada-385-linksys-rango.dts | 25 wan_white@1 {
86 #address-cells = <1>;
87 #size-cells = <1>;
97 reg = <0x200000 0x20000>; /* 128KiB */
102 reg = <0x220000 0x40000>; /* 256KiB */
107 reg = <0x7e0000 0x40000>; /* 256KiB */
113 reg = <0x820000 0x1e0000>; /* 1920KiB */
163 no-1-8-v;
|
| /kernel/linux/linux-5.10/drivers/mtd/nand/onenand/ |
| D | Kconfig | 16 from 1 to 0. There is a rare possibility that even though the
47 Also, 1st Block of NAND Flash Array can be used as OTP.
61 of 4KiB. Plane1 has only even blocks such as block0, block2, block4
63 So MTD regards it as 4KiB page size and 256KiB block size
|
| /kernel/linux/linux-6.6/drivers/mtd/nand/onenand/ |
| D | Kconfig | 16 from 1 to 0. There is a rare possibility that even though the
49 Also, 1st Block of NAND Flash Array can be used as OTP.
63 of 4KiB. Plane1 has only even blocks such as block0, block2, block4
65 So MTD regards it as 4KiB page size and 256KiB block size
|