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/kernel/linux/linux-5.10/drivers/gpu/drm/i915/gt/
Dintel_gpu_commands.h2 * SPDX-License-Identifier: MIT
4 * Copyright � 2003-2018 Intel Corporation
22 #define INSTR_CLIENT_SHIFT 29
30 #define INSTR_26_TO_24_SHIFT 24
134 * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
136 * - One can actually load arbitrary many arbitrary registers: Simply issue x
139 #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*(x)-1)
175 #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
177 #define GEN9_MEDIA_POOL_STATE ((0x3 << 29) | (0x2 << 27) | (0x5 << 16) | 4)
179 #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
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/kernel/linux/linux-6.6/arch/powerpc/crypto/
Daes-gcm-p10.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 # Accelerated AES-GCM stitched implementation for ppc64le.
5 # Copyright 2022- IBM Inc. All rights reserved
22 # Hash keys = v3 - v14
29 # v31 - counter 1
32 # vs0 - vs14 for round keys
35 # This implementation uses stitched AES-GCM approach to improve overall performance.
48 # v15 - v18 - input states
49 # vs1 - vs9 - round keys
110 # v15 - v22 - input states
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Dpoly1305-p10le_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
10 # Poly1305 - this version mainly using vector/VSX/Scalar
11 # - 26 bits limbs
12 # - Handle multiple 64 byte blcok.
17 # p = 2^130 - 5
25 # 07/22/21 - this revison based on the above sum of products. Setup r^4, r^3, r^2, r and s3, s2, …
56 #include <asm/asm-offsets.h>
57 #include <asm/asm-compat.h>
95 stdu 1,-752(1)
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Dchacha-p10le-8x.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
43 #include <asm/asm-offsets.h>
44 #include <asm/asm-compat.h>
81 stdu 1,-752(1)
93 SAVE_GPR 24, 192, 1
98 SAVE_GPR 29, 232, 1
107 SAVE_VRS 24, 64, 9
112 SAVE_VRS 29, 144, 9
126 SAVE_VSX 24, 352, 9
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/kernel/linux/linux-6.6/drivers/gpu/drm/i915/gt/
Dintel_gpu_commands.h1 /* SPDX-License-Identifier: MIT*/
3 * Copyright © 2003-2018 Intel Corporation
21 #define INSTR_CLIENT_SHIFT 29
30 #define INSTR_26_TO_24_SHIFT 24
150 * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
152 * - One can actually load arbitrary many arbitrary registers: Simply issue x
155 #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*(x)-1)
199 #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
201 #define GEN9_MEDIA_POOL_STATE ((0x3 << 29) | (0x2 << 27) | (0x5 << 16) | 4)
203 #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/
Dintel_backlight_regs.h1 /* SPDX-License-Identifier: MIT */
27 #define BLM_PIPE_SELECT (1 << 29)
28 #define BLM_PIPE_SELECT_IVB (3 << 29)
29 #define BLM_PIPE_A (0 << 29)
30 #define BLM_PIPE_B (1 << 29)
31 #define BLM_PIPE_C (2 << 29) /* ivb + */
35 #define BLM_TRANSCODER_EDP (3 << 29)
36 #define BLM_PIPE(pipe) ((pipe) << 29)
40 #define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24)
72 /* New registers for PCH-split platforms. Safe where new bits show up, the
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/kernel/linux/linux-6.6/Documentation/translations/zh_CN/core-api/
Dpacking.rst1 .. SPDX-License-Identifier: GPL-2.0+
3 .. include:: ../disclaimer-zh_CN.rst
5 :Original: Documentation/core-api/packing.rst
22 --------
42 --------
46 - 将一个CPU可使用的数字打包到内存缓冲区中（具有硬件约束/特殊性）。
47 - 将内存缓冲区（具有硬件约束/特殊性）解压缩为一个CPU可使用的数字。
63 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
77 24 25 26 27 28 29 30 31 16 17 18 19 20 21 22 23 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7
89 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 31 30 29 28 27 26 25 24
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/kernel/linux/linux-5.10/drivers/gpu/drm/i810/
Di810_drv.h1 /* i810_drv.h -- Private header for the Matrox g200/g400 driver -*- linux-c -*-
50 * 1.1 - XFree86 4.1
51 * 1.2 - XvMC interfaces
52 * - XFree86 4.2
53 * 1.2.1 - Disable copying code (leave stub ioctls for backwards compatibility)
54 * - Remove requirement for interrupt (leave stubs again)
55 * 1.3 - Add page flipping.
56 * 1.4 - fix DRM interface
135 dev_priv->mmio_map->handle)
151 if (dev_priv->ring.space < n*4) \
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/kernel/linux/linux-6.6/drivers/net/wireless/mediatek/mt76/
Dmt76_connac2_mac.h1 /* SPDX-License-Identifier: ISC */
46 #define MT_TXD0_PKT_FMT GENMASK(24, 23)
52 #define MT_TXD1_OWN_MAC GENMASK(29, 24)
64 #define MT_TXD2_POWER_OFFSET GENMASK(29, 24)
80 #define MT_TXD3_SW_POWER_MGMT BIT(29)
104 #define MT_TXD6_TX_RATE GENMASK(29, 16)
115 #define MT_TXD7_UDP_TCP_SUM BIT(29)
133 /* VHT/HE only use bits 0-3 */
137 #define MT_TXS0_BW GENMASK(30, 29)
140 #define MT_TXS0_TXS_FORMAT GENMASK(24, 23)
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Dmt76_connac3_mac.h1 /* SPDX-License-Identifier: ISC */
32 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
47 #define MT_RXD1_NORMAL_CLM BIT(24)
51 #define MT_RXD1_NORMAL_SPP_EN BIT(29)
64 #define MT_RXD2_NORMAL_MAX_LEN_ERROR BIT(24)
69 #define MT_RXD2_NORMAL_NDATA BIT(29)
82 #define MT_RXD3_NORMAL_FCS_ERR BIT(24)
91 #define MT_RXV_HDR_BAND_IDX BIT(24)
101 /* P-RXV */
109 #define MT_PRXV_RCPI3 GENMASK(31, 24)
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/kernel/linux/linux-5.10/include/linux/netfilter/
Dnf_conntrack_h323_types.h1 /* SPDX-License-Identifier: GPL-2.0-only */
140 eH2250LogicalChannelParameters_mediaChannel = (1 << 29),
148 eH2250LogicalChannelParameters_destination = (1 << 24),
181 = (1 << 29),
206 = (1 << 29),
227 eNetworkAccessParameters_t120SetupProcedure = (1 << 29),
237 eOpenLogicalChannel_encryptionSync = (1 << 29),
255 eSetup_UUIE_destinationAddress = (1 << 29),
260 eSetup_UUIE_sourceCallSignalAddress = (1 << 24),
301 eCallProceeding_UUIE_h245SecurityMode = (1 << 29),
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/kernel/linux/linux-6.6/include/linux/netfilter/
Dnf_conntrack_h323_types.h1 /* SPDX-License-Identifier: GPL-2.0-only */
140 eH2250LogicalChannelParameters_mediaChannel = (1 << 29),
148 eH2250LogicalChannelParameters_destination = (1 << 24),
181 = (1 << 29),
206 = (1 << 29),
227 eNetworkAccessParameters_t120SetupProcedure = (1 << 29),
237 eOpenLogicalChannel_encryptionSync = (1 << 29),
255 eSetup_UUIE_destinationAddress = (1 << 29),
260 eSetup_UUIE_sourceCallSignalAddress = (1 << 24),
301 eCallProceeding_UUIE_h245SecurityMode = (1 << 29),
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/kernel/linux/linux-6.6/drivers/net/wireless/mediatek/mt76/mt7615/
Dmac.h1 /* SPDX-License-Identifier: ISC */
12 #define MT_RXD0_PKT_TYPE GENMASK(31, 29)
16 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
23 #define MT_RXD1_NORMAL_PAYLOAD_FORMAT GENMASK(25, 24)
43 #define MT_RXD2_NORMAL_NDATA BIT(29)
48 #define MT_RXD2_NORMAL_MAX_LEN_ERROR BIT(24)
62 #define MT_RXD3_NORMAL_PF_MODE BIT(29)
81 #define MT_RXV1_VHTA2_B8_B3 GENMASK(29, 24)
97 #define MT_RXV2_NSTS GENMASK(29, 27)
101 #define MT_RXV3_WB_RSSI GENMASK(31, 24)
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/kernel/linux/linux-5.10/drivers/staging/media/zoran/
Dzr36057.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * zr36057.h - zr36057 register offsets
28 #define ZR36057_VFESPFR_VCLK_POL BIT(24)
53 #define ZR36057_VDCR_MIN_PIX 24
54 #define ZR36057_VDCR_TRITON BIT(24)
67 #define ZR36057_SPGPPCR_SOFT_RESET BIT(24)
75 #define ZR36057_MCTCR_C_EMPTY BIT(29)
84 #define ZR36057_ISR_GIRQ0 BIT(29)
90 #define ZR36057_ICR_GIRQ0 BIT(29)
93 #define ZR36057_ICR_INT_PIN_EN BIT(24)
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/kernel/linux/linux-6.6/drivers/media/pci/zoran/
Dzr36057.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * zr36057.h - zr36057 register offsets
28 #define ZR36057_VFESPFR_VCLK_POL BIT(24)
53 #define ZR36057_VDCR_MIN_PIX 24
54 #define ZR36057_VDCR_TRITON BIT(24)
67 #define ZR36057_SPGPPCR_SOFT_RESET BIT(24)
75 #define ZR36057_MCTCR_C_EMPTY BIT(29)
84 #define ZR36057_ISR_GIRQ0 BIT(29)
90 #define ZR36057_ICR_GIRQ0 BIT(29)
93 #define ZR36057_ICR_INT_PIN_EN BIT(24)
[all …]
/kernel/linux/linux-6.6/drivers/net/wireless/mediatek/mt76/mt7603/
Dmac.h1 /* SPDX-License-Identifier: ISC */
7 #define MT_RXD0_PKT_TYPE GENMASK(31, 29)
11 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
28 #define MT_RXD1_NORMAL_PAYLOAD_FORMAT GENMASK(25, 24)
43 #define MT_RXD2_NORMAL_NDATA BIT(29)
48 #define MT_RXD2_NORMAL_MAX_LEN_ERROR BIT(24)
62 #define MT_RXD3_NORMAL_PF_MODE BIT(29)
73 #define MT_RXV1_VHTA2_B8_B1 GENMASK(29, 22)
89 #define MT_RXV3_F_AGC1_CAL_GAIN GENMASK(31, 29)
100 #define MT_RXV4_F_AGC_CAL_GAIN GENMASK(31, 29)
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/kernel/linux/linux-5.10/drivers/net/wireless/mediatek/mt76/mt7603/
Dmac.h1 /* SPDX-License-Identifier: ISC */
7 #define MT_RXD0_PKT_TYPE GENMASK(31, 29)
11 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
28 #define MT_RXD1_NORMAL_PAYLOAD_FORMAT GENMASK(25, 24)
43 #define MT_RXD2_NORMAL_NDATA BIT(29)
48 #define MT_RXD2_NORMAL_MAX_LEN_ERROR BIT(24)
62 #define MT_RXD3_NORMAL_PF_MODE BIT(29)
73 #define MT_RXV1_VHTA2_B8_B1 GENMASK(29, 22)
89 #define MT_RXV3_F_AGC1_CAL_GAIN GENMASK(31, 29)
100 #define MT_RXV4_F_AGC_CAL_GAIN GENMASK(31, 29)
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/kernel/linux/linux-5.10/drivers/net/ethernet/broadcom/bnxt/
Dbnxt_hsi.h1 /* Broadcom NetXtreme-C/E network driver.
3 * Copyright (c) 2014-2016 Broadcom Corporation
4 * Copyright (c) 2014-2018 Broadcom Limited
5 * Copyright (c) 2018-2020 Broadcom Inc.
477 #define HWRM_NA_SIGNATURE ((__le32)(-1))
493 /* hwrm_ver_get_input (size:192b/24B) */
1036 /* hwrm_func_reset_input (size:192b/24B) */
1065 /* hwrm_func_getfid_input (size:192b/24B) */
1089 /* hwrm_func_vf_alloc_input (size:192b/24B) */
1113 /* hwrm_func_vf_free_input (size:192b/24B) */
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/exynos/
Dregs-scaler.h1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* drivers/gpu/drm/exynos/regs-scaler.h
127 #define SCALER_MASK(hi_b, lo_b) ((1 << ((hi_b) - (lo_b) + 1)) - 1)
138 #define SCALER_CFG_FILL_EN (1 << 24)
149 #define SCALER_INT_EN_ILLEGAL_BLEND (1 << 24)
177 #define SCALER_INT_STATUS_ILLEGAL_BLEND (1 << 24)
231 #define SCALER_SRC_SPAN_GET_C_SPAN(r) SCALER_GET(r, 29, 16)
232 #define SCALER_SRC_SPAN_SET_C_SPAN(v) SCALER_SET(v, 29, 16)
243 #define SCALER_SRC_WH_GET_WIDTH(r) SCALER_GET(r, 29, 16)
244 #define SCALER_SRC_WH_SET_WIDTH(v) SCALER_SET(v, 29, 16)
[all …]
Dregs-fimc.h1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* drivers/gpu/drm/exynos/regs-fimc.h
52 /* Pre-scaler control 1 */
54 /* Pre-scaler control 2 */
158 /* Y 24th frame start address for output DMA */
168 /* Y 29th frame start address for output DMA */
215 /* CB 24th frame start address for output DMA */
225 /* CB 29th frame start address for output DMA */
272 /* CR 24th frame start address for output DMA */
282 /* CR 29th frame start address for output DMA */
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/exynos/
Dregs-scaler.h1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* drivers/gpu/drm/exynos/regs-scaler.h
127 #define SCALER_MASK(hi_b, lo_b) ((1 << ((hi_b) - (lo_b) + 1)) - 1)
138 #define SCALER_CFG_FILL_EN (1 << 24)
149 #define SCALER_INT_EN_ILLEGAL_BLEND (1 << 24)
177 #define SCALER_INT_STATUS_ILLEGAL_BLEND (1 << 24)
231 #define SCALER_SRC_SPAN_GET_C_SPAN(r) SCALER_GET(r, 29, 16)
232 #define SCALER_SRC_SPAN_SET_C_SPAN(v) SCALER_SET(v, 29, 16)
243 #define SCALER_SRC_WH_GET_WIDTH(r) SCALER_GET(r, 29, 16)
244 #define SCALER_SRC_WH_SET_WIDTH(v) SCALER_SET(v, 29, 16)
[all …]
Dregs-fimc.h1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* drivers/gpu/drm/exynos/regs-fimc.h
52 /* Pre-scaler control 1 */
54 /* Pre-scaler control 2 */
158 /* Y 24th frame start address for output DMA */
168 /* Y 29th frame start address for output DMA */
215 /* CB 24th frame start address for output DMA */
225 /* CB 29th frame start address for output DMA */
272 /* CR 24th frame start address for output DMA */
282 /* CR 29th frame start address for output DMA */
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/mediatek/mt76/mt7615/
Dmac.h1 /* SPDX-License-Identifier: ISC */
12 #define MT_RXD0_PKT_TYPE GENMASK(31, 29)
16 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
35 #define MT_RXD1_NORMAL_PAYLOAD_FORMAT GENMASK(25, 24)
52 #define MT_RXD2_NORMAL_NDATA BIT(29)
57 #define MT_RXD2_NORMAL_MAX_LEN_ERROR BIT(24)
71 #define MT_RXD3_NORMAL_PF_MODE BIT(29)
83 #define MT_RXV1_VHTA2_B8_B3 GENMASK(29, 24)
99 #define MT_RXV2_NSTS GENMASK(29, 27)
103 #define MT_RXV3_WB_RSSI GENMASK(31, 24)
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/mediatek/mt76/mt7915/
Dmac.h1 /* SPDX-License-Identifier: ISC */
15 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
38 #define MT_RXD1_NORMAL_CLM BIT(24)
43 #define MT_RXD1_NORMAL_SPP_EN BIT(29)
58 #define MT_RXD2_NORMAL_MAX_LEN_ERROR BIT(24)
63 #define MT_RXD2_NORMAL_NDATA BIT(29)
78 #define MT_RXD3_NORMAL_MHCP BIT(24)
83 #define MT_RXD3_NORMAL_UNWANT BIT(29)
95 #define MT_RXD3_NORMAL_PF_MODE BIT(29)
98 /* P-RXV */
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/kernel/linux/linux-5.10/Documentation/core-api/
Dpacking.rst6 -----------------
10 One can memory-map a pointer to a carefully crafted struct over the hardware
23 were performed byte-by-byte. Also the code can easily get cluttered, and the
24 high-level idea might get lost among the many bit shifts required.
25 Many drivers take the bit-shifting approach and then attempt to reduce the
30 ------------
34 - Packing a CPU-usable number into a memory buffer (with hardware
36 - Unpacking a memory buffer (which has hardware constraints/quirks)
37 into a CPU-usable number.
57 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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